URL https://opencores.org/ocsvn/sata_controller_core/sata_controller_core/trunk

Subversion Repositories sata_controller_core

[/] [sata_controller_core/] [trunk/] [sata2_bus_v1_00_a/] [base_system/] [pcores/] [sata_core_v1_00_a/] [hdl/] [verilog/] [mux_21.v] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	ashwin_men	`//--------------------------------------------------------------------------------`
2			`// Entity mux_21`
3			`// Version: 1.0`
4			`// Author: Ashwin Mendon`
5			`// Description: 2 bit 2:1 Multiplexer`
6			`//--------------------------------------------------------------------------------`
7
8			`module mux_21`
9			`(`
10			`input wire [1:0] a,`
11			`input wire [1:0] b,`
12			`input wire sel,`
13			`output reg [1:0] o`
14			`);`
15
16			`always @ (a or b or sel)`
17			`begin`
18			`case (sel)`
19			`1'b0:`
20			`o = a;`
21			`1'b1:`
22			`o = b;`
23			`endcase`
24			`end`
25
26			`endmodule`
27