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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version : 1.8
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// \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard
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// / / Filename : sata_gtx.v
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// /___/ /\ Timestamp :
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// \ \ / \
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// \___\/\___\
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//
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//
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// Module SATA_GTX (a GTX Wrapper)
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// Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
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//
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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`timescale 1ns / 1ps
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//***************************** Entity Declaration ****************************
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module SATA_GTX #
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(
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// Simulation attributes
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parameter GTX_SIM_GTXRESET_SPEEDUP = 0, // Set to 1 to speed up sim reset
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// Share RX PLL parameter
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parameter GTX_TX_CLK_SOURCE = "TXPLL",
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// Save power parameter
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parameter GTX_POWER_SAVE = 10'b0000000000
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)
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(
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//---------------------- Loopback and Powerdown Ports ----------------------
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input [2:0] LOOPBACK_IN,
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//--------------------- Receive Ports - 8b10b Decoder ----------------------
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output [3:0] RXCHARISK_OUT,
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output [3:0] RXDISPERR_OUT,
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output [3:0] RXNOTINTABLE_OUT,
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//----------------- Receive Ports - Clock Correction Ports -----------------
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output [2:0] RXCLKCORCNT_OUT,
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//------------- Receive Ports - Comma Detection and Alignment --------------
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output RXBYTEISALIGNED_OUT,
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output RXBYTEREALIGN_OUT,
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input RXENMCOMMAALIGN_IN,
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input RXENPCOMMAALIGN_IN,
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//----------------- Receive Ports - RX Data Path interface -----------------
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output [31:0] RXDATA_OUT,
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output RXRECCLK_OUT,
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input RXRESET_IN,
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input RXUSRCLK_IN,
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input RXUSRCLK2_IN,
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//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
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output RXELECIDLE_OUT,
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input [2:0] RXEQMIX_IN,
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input RXN_IN,
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input RXP_IN,
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//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
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input RXBUFRESET_IN,
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output [2:0] RXSTATUS_OUT,
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//---------------------- Receive Ports - RX PLL Ports ----------------------
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input GTXRXRESET_IN,
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input [1:0] MGTREFCLKRX_IN,
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input PLLRXRESET_IN,
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output RXPLLLKDET_OUT,
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output RXRESETDONE_OUT,
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//------------------- Receive Ports - RX Ports for SATA --------------------
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output COMINITDET_OUT,
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output COMWAKEDET_OUT,
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// -------------- Speed Neg Module ports ------------------------
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input [6:0] DADDR, //DRP address
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input DEN, //DRP enable
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input [15:0] DI, //DRP data in
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output[15:0] DO, //DRP data out
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output DRDY, //DRP ready
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input DWE, //DRP write enable
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input DCLK,
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//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
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input [3:0] TXCHARISK_IN,
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//---------------- Transmit Ports - TX Data Path interface -----------------
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input [31:0] TXDATA_IN,
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output TXOUTCLK_OUT,
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input TXRESET_IN,
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input TXUSRCLK_IN,
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input TXUSRCLK2_IN,
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//-------------- Transmit Ports - TX Driver and OOB signaling --------------
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input [3:0] TXDIFFCTRL_IN,
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output TXN_OUT,
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output TXP_OUT,
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input [4:0] TXPOSTEMPHASIS_IN,
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//------------- Transmit Ports - TX Driver and OOB signalling --------------
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input [3:0] TXPREEMPHASIS_IN,
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//--------------------- Transmit Ports - TX PLL Ports ----------------------
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input GTXTXRESET_IN,
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input [1:0] MGTREFCLKTX_IN,
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input PLLTXRESET_IN,
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output TXPLLLKDET_OUT,
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output TXRESETDONE_OUT,
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//--------------- Transmit Ports - TX Ports for PCI Express ----------------
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input TXELECIDLE_IN,
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//------------------- Transmit Ports - TX Ports for SATA -------------------
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output COMFINISH_OUT,
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input TXCOMINIT_IN,
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input TXCOMWAKE_IN
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);
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//***************************** Wire Declarations *****************************
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// ground and vcc signals
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wire tied_to_ground_i;
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wire [63:0] tied_to_ground_vec_i;
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wire tied_to_vcc_i;
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wire [63:0] tied_to_vcc_vec_i;
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//RX Datapath signals
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wire [31:0] rxdata_i;
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//TX Datapath signals
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wire [31:0] txdata_i;
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//
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//********************************* Main Body of Code**************************
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//------------------------- Static signal Assigments ---------------------
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assign tied_to_ground_i = 1'b0;
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assign tied_to_ground_vec_i = 64'h0000000000000000;
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assign tied_to_vcc_i = 1'b1;
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assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
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//------------------- GTX Datapath byte mapping -----------------
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// The GTX provides little endian data (first byte received on RXDATA[7:0])
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assign RXDATA_OUT = rxdata_i;
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// The GTX transmits little endian data (TXDATA[7:0] transmitted first)
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assign txdata_i = TXDATA_IN;
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//------------------------- GTX Instantiations --------------------------
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GTXE1 #
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(
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//_______________________ Simulation-Only Attributes __________________
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//.SIM_RECEIVER_DETECT_PASS ("TRUE"),
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//.SIM_TX_ELEC_IDLE_LEVEL ("X"),
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//.SIM_GTXRESET_SPEEDUP (GTX_SIM_GTXRESET_SPEEDUP),
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//.SIM_VERSION ("2.0"),
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//.SIM_TXREFCLK_SOURCE (3'b000),
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//.SIM_RXREFCLK_SOURCE (3'b000),
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//--------------------------TX PLL----------------------------
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.TX_CLK_SOURCE (GTX_TX_CLK_SOURCE),
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.TX_OVERSAMPLE_MODE ("FALSE"),
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.TXPLL_COM_CFG (24'h21680a),
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.TXPLL_CP_CFG (8'h0D),
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.TXPLL_DIVSEL_FB (2),
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.TXPLL_DIVSEL_OUT (1),
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.TXPLL_DIVSEL_REF (1),
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.TXPLL_DIVSEL45_FB (5),
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.TXPLL_LKDET_CFG (3'b111),
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.TX_CLK25_DIVIDER (6),
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.TXPLL_SATA (2'b01),
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.TX_TDCC_CFG (2'b11),
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.PMA_CAS_CLK_EN ("FALSE"),
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.POWER_SAVE (GTX_POWER_SAVE),
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//-----------------------TX Interface-------------------------
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.GEN_TXUSRCLK ("FALSE"),
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.TX_DATA_WIDTH (40),
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.TX_USRCLK_CFG (6'h00),
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//.TXOUTCLK_CTRL ("TXOUTCLKPMA_DIV2"),
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.TXOUTCLK_CTRL ("TXPLLREFCLK_DIV2"),
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.TXOUTCLK_DLY (10'b0000000000),
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//------------TX Buffering and Phase Alignment----------------
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.TX_PMADATA_OPT (1'b0),
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.PMA_TX_CFG (20'h80082),
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.TX_BUFFER_USE ("TRUE"),
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.TX_BYTECLK_CFG (6'h00),
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.TX_EN_RATE_RESET_BUF ("TRUE"),
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.TX_XCLK_SEL ("TXOUT"),
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.TX_DLYALIGN_CTRINC (4'b0100),
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.TX_DLYALIGN_LPFINC (4'b0110),
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.TX_DLYALIGN_MONSEL (3'b000),
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.TX_DLYALIGN_OVRDSETTING (8'b10000000),
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//-----------------------TX Gearbox---------------------------
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.GEARBOX_ENDEC (3'b000),
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.TXGEARBOX_USE ("FALSE"),
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//--------------TX Driver and OOB Signalling------------------
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.TX_DRIVE_MODE ("DIRECT"),
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.TX_IDLE_ASSERT_DELAY (3'b100),
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.TX_IDLE_DEASSERT_DELAY (3'b010),
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.TXDRIVE_LOOPBACK_HIZ ("FALSE"),
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.TXDRIVE_LOOPBACK_PD ("FALSE"),
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//------------TX Pipe Control for PCI Express/SATA------------
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.COM_BURST_VAL (4'b0101),
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//----------------TX Attributes for PCI Express---------------
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.TX_DEEMPH_0 (5'b11010),
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.TX_DEEMPH_1 (5'b10000),
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.TX_MARGIN_FULL_0 (7'b1001110),
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.TX_MARGIN_FULL_1 (7'b1001001),
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.TX_MARGIN_FULL_2 (7'b1000101),
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.TX_MARGIN_FULL_3 (7'b1000010),
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.TX_MARGIN_FULL_4 (7'b1000000),
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.TX_MARGIN_LOW_0 (7'b1000110),
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.TX_MARGIN_LOW_1 (7'b1000100),
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.TX_MARGIN_LOW_2 (7'b1000010),
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.TX_MARGIN_LOW_3 (7'b1000000),
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.TX_MARGIN_LOW_4 (7'b1000000),
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//--------------------------RX PLL----------------------------
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.RX_OVERSAMPLE_MODE ("FALSE"),
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.RXPLL_COM_CFG (24'h21680a),
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.RXPLL_CP_CFG (8'h0D),
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.RXPLL_DIVSEL_FB (2),
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.RXPLL_DIVSEL_OUT (1),
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.RXPLL_DIVSEL_REF (1),
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.RXPLL_DIVSEL45_FB (5),
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.RXPLL_LKDET_CFG (3'b111),
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.RX_CLK25_DIVIDER (6),
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//-----------------------RX Interface-------------------------
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.GEN_RXUSRCLK ("FALSE"),
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.RX_DATA_WIDTH (40),
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.RXRECCLK_CTRL ("RXRECCLKPMA_DIV2"),
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.RXRECCLK_DLY (10'b0000000000),
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.RXUSRCLK_DLY (16'h0000),
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//--------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
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.AC_CAP_DIS ("FALSE"),
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.CDR_PH_ADJ_TIME (5'b10100),
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.OOBDETECT_THRESHOLD (3'b111),
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//.PMA_CDR_SCAN (27'h640404C),
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.PMA_CDR_SCAN (27'h6C08040),
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//.PMA_RX_CFG (25'h05ce049),
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.PMA_RX_CFG (25'h0DCE111),
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.RCV_TERM_GND ("FALSE"),
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.RCV_TERM_VTTRX ("TRUE"),
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.RX_EN_IDLE_HOLD_CDR ("FALSE"),
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.RX_EN_IDLE_RESET_FR ("TRUE"),
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.RX_EN_IDLE_RESET_PH ("TRUE"),
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.TX_DETECT_RX_CFG (14'h1832),
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.TERMINATION_CTRL (5'b00000),
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.TERMINATION_OVRD ("FALSE"),
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.CM_TRIM (2'b01),
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.PMA_RXSYNC_CFG (7'h00),
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.PMA_CFG (76'h0040000040000000003),
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.BGTEST_CFG (2'b00),
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.BIAS_CFG (17'h00000),
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//------------RX Decision Feedback Equalizer(DFE)-------------
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.DFE_CAL_TIME (5'b01100),
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.DFE_CFG (8'b00011011),
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.RX_EN_IDLE_HOLD_DFE ("TRUE"),
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.RX_EYE_OFFSET (8'h4C),
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.RX_EYE_SCANMODE (2'b00),
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| 320 |
|
|
//-----------------------PRBS Detection-----------------------
|
| 321 |
|
|
.RXPRBSERR_LOOPBACK (1'b0),
|
| 322 |
|
|
|
| 323 |
|
|
//----------------Comma Detection and Alignment---------------
|
| 324 |
|
|
.ALIGN_COMMA_WORD (2),
|
| 325 |
|
|
.COMMA_10B_ENABLE (10'b1111111111),
|
| 326 |
|
|
.COMMA_DOUBLE ("FALSE"),
|
| 327 |
|
|
.DEC_MCOMMA_DETECT ("TRUE"), //changed
|
| 328 |
|
|
.DEC_PCOMMA_DETECT ("TRUE"), //changed
|
| 329 |
|
|
.DEC_VALID_COMMA_ONLY ("FALSE"),
|
| 330 |
|
|
//.MCOMMA_10B_VALUE (10'b0110000011),
|
| 331 |
|
|
.MCOMMA_10B_VALUE (10'b1010000011),
|
| 332 |
|
|
.MCOMMA_DETECT ("TRUE"),
|
| 333 |
|
|
.PCOMMA_10B_VALUE (10'b0101111100),
|
| 334 |
|
|
.PCOMMA_DETECT ("TRUE"),
|
| 335 |
|
|
.RX_DECODE_SEQ_MATCH ("TRUE"),
|
| 336 |
|
|
.RX_SLIDE_AUTO_WAIT (5),
|
| 337 |
|
|
//.RX_SLIDE_MODE ("OFF"),
|
| 338 |
|
|
.RX_SLIDE_MODE ("PCS"),
|
| 339 |
|
|
.SHOW_REALIGN_COMMA ("FALSE"),
|
| 340 |
|
|
|
| 341 |
|
|
//---------------RX Loss-of-sync State Machine----------------
|
| 342 |
|
|
.RX_LOS_INVALID_INCR (8),
|
| 343 |
|
|
.RX_LOS_THRESHOLD (128),
|
| 344 |
|
|
.RX_LOSS_OF_SYNC_FSM ("FALSE"),
|
| 345 |
|
|
|
| 346 |
|
|
//-----------------------RX Gearbox---------------------------
|
| 347 |
|
|
.RXGEARBOX_USE ("FALSE"),
|
| 348 |
|
|
|
| 349 |
|
|
//-----------RX Elastic Buffer and Phase alignment------------
|
| 350 |
|
|
.RX_BUFFER_USE ("TRUE"),
|
| 351 |
|
|
.RX_EN_IDLE_RESET_BUF ("TRUE"),
|
| 352 |
|
|
.RX_EN_MODE_RESET_BUF ("TRUE"),
|
| 353 |
|
|
.RX_EN_RATE_RESET_BUF ("TRUE"),
|
| 354 |
|
|
.RX_EN_REALIGN_RESET_BUF ("FALSE"),
|
| 355 |
|
|
.RX_EN_REALIGN_RESET_BUF2 ("FALSE"),
|
| 356 |
|
|
.RX_FIFO_ADDR_MODE ("FULL"),
|
| 357 |
|
|
.RX_IDLE_HI_CNT (4'b1000),
|
| 358 |
|
|
.RX_IDLE_LO_CNT (4'b0000),
|
| 359 |
|
|
.RX_XCLK_SEL ("RXREC"),
|
| 360 |
|
|
.RX_DLYALIGN_CTRINC (4'b1110),
|
| 361 |
|
|
.RX_DLYALIGN_EDGESET (5'b00010),
|
| 362 |
|
|
.RX_DLYALIGN_LPFINC (4'b1110),
|
| 363 |
|
|
.RX_DLYALIGN_MONSEL (3'b000),
|
| 364 |
|
|
.RX_DLYALIGN_OVRDSETTING (8'b10000000),
|
| 365 |
|
|
|
| 366 |
|
|
//----------------------Clock Correction----------------------
|
| 367 |
|
|
.CLK_COR_ADJ_LEN (4),
|
| 368 |
|
|
.CLK_COR_DET_LEN (4),
|
| 369 |
|
|
.CLK_COR_INSERT_IDLE_FLAG ("FALSE"),
|
| 370 |
|
|
.CLK_COR_KEEP_IDLE ("FALSE"),
|
| 371 |
|
|
//.CLK_COR_MAX_LAT (20),
|
| 372 |
|
|
.CLK_COR_MAX_LAT (18),
|
| 373 |
|
|
//.CLK_COR_MIN_LAT (14),
|
| 374 |
|
|
.CLK_COR_MIN_LAT (16),
|
| 375 |
|
|
.CLK_COR_PRECEDENCE ("TRUE"),
|
| 376 |
|
|
.CLK_COR_REPEAT_WAIT (0),
|
| 377 |
|
|
.CLK_COR_SEQ_1_1 (10'b0110111100),
|
| 378 |
|
|
.CLK_COR_SEQ_1_2 (10'b0001001010),
|
| 379 |
|
|
.CLK_COR_SEQ_1_3 (10'b0001001010),
|
| 380 |
|
|
.CLK_COR_SEQ_1_4 (10'b0001111011),
|
| 381 |
|
|
.CLK_COR_SEQ_1_ENABLE (4'b1111),
|
| 382 |
|
|
.CLK_COR_SEQ_2_1 (10'b0100000000),
|
| 383 |
|
|
.CLK_COR_SEQ_2_2 (10'b0100000000),
|
| 384 |
|
|
.CLK_COR_SEQ_2_3 (10'b0100000000),
|
| 385 |
|
|
.CLK_COR_SEQ_2_4 (10'b0100000000),
|
| 386 |
|
|
//.CLK_COR_SEQ_2_ENABLE (4'b1111),
|
| 387 |
|
|
.CLK_COR_SEQ_2_ENABLE (4'b0000),
|
| 388 |
|
|
.CLK_COR_SEQ_2_USE ("FALSE"),
|
| 389 |
|
|
.CLK_CORRECT_USE ("TRUE"),
|
| 390 |
|
|
|
| 391 |
|
|
//----------------------Channel Bonding----------------------
|
| 392 |
|
|
.CHAN_BOND_1_MAX_SKEW (1),
|
| 393 |
|
|
.CHAN_BOND_2_MAX_SKEW (1),
|
| 394 |
|
|
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
|
| 395 |
|
|
.CHAN_BOND_SEQ_1_1 (10'b0000000000),
|
| 396 |
|
|
.CHAN_BOND_SEQ_1_2 (10'b0000000000),
|
| 397 |
|
|
.CHAN_BOND_SEQ_1_3 (10'b0000000000),
|
| 398 |
|
|
.CHAN_BOND_SEQ_1_4 (10'b0000000000),
|
| 399 |
|
|
.CHAN_BOND_SEQ_1_ENABLE (4'b1111),
|
| 400 |
|
|
.CHAN_BOND_SEQ_2_1 (10'b0000000000),
|
| 401 |
|
|
.CHAN_BOND_SEQ_2_2 (10'b0000000000),
|
| 402 |
|
|
.CHAN_BOND_SEQ_2_3 (10'b0000000000),
|
| 403 |
|
|
.CHAN_BOND_SEQ_2_4 (10'b0000000000),
|
| 404 |
|
|
.CHAN_BOND_SEQ_2_CFG (5'b00000),
|
| 405 |
|
|
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
|
| 406 |
|
|
.CHAN_BOND_SEQ_2_USE ("FALSE"),
|
| 407 |
|
|
.CHAN_BOND_SEQ_LEN (1),
|
| 408 |
|
|
.PCI_EXPRESS_MODE ("FALSE"),
|
| 409 |
|
|
|
| 410 |
|
|
//-----------RX Attributes for PCI Express/SATA/SAS----------
|
| 411 |
|
|
.SAS_MAX_COMSAS (52),
|
| 412 |
|
|
.SAS_MIN_COMSAS (40),
|
| 413 |
|
|
.SATA_BURST_VAL (3'b100),
|
| 414 |
|
|
.SATA_IDLE_VAL (3'b100),
|
| 415 |
|
|
.SATA_MAX_BURST (7),
|
| 416 |
|
|
.SATA_MAX_INIT (22),
|
| 417 |
|
|
.SATA_MAX_WAKE (7),
|
| 418 |
|
|
.SATA_MIN_BURST (4),
|
| 419 |
|
|
.SATA_MIN_INIT (12),
|
| 420 |
|
|
.SATA_MIN_WAKE (4),
|
| 421 |
|
|
.TRANS_TIME_FROM_P2 (12'h03c),
|
| 422 |
|
|
.TRANS_TIME_NON_P2 (8'h19),
|
| 423 |
|
|
.TRANS_TIME_RATE (8'hff),
|
| 424 |
|
|
.TRANS_TIME_TO_P2 (10'h064)
|
| 425 |
|
|
|
| 426 |
|
|
|
| 427 |
|
|
)
|
| 428 |
|
|
gtxe1_i
|
| 429 |
|
|
(
|
| 430 |
|
|
|
| 431 |
|
|
//---------------------- Loopback and Powerdown Ports ----------------------
|
| 432 |
|
|
.LOOPBACK (LOOPBACK_IN),
|
| 433 |
|
|
.RXPOWERDOWN (2'b00),
|
| 434 |
|
|
.TXPOWERDOWN (2'b00),
|
| 435 |
|
|
//------------ Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
|
| 436 |
|
|
.RXDATAVALID (),
|
| 437 |
|
|
.RXGEARBOXSLIP (tied_to_ground_i),
|
| 438 |
|
|
.RXHEADER (),
|
| 439 |
|
|
.RXHEADERVALID (),
|
| 440 |
|
|
.RXSTARTOFSEQ (),
|
| 441 |
|
|
//--------------------- Receive Ports - 8b10b Decoder ----------------------
|
| 442 |
|
|
.RXCHARISCOMMA (),
|
| 443 |
|
|
.RXCHARISK (RXCHARISK_OUT),
|
| 444 |
|
|
.RXDEC8B10BUSE (tied_to_vcc_i),
|
| 445 |
|
|
.RXDISPERR (RXDISPERR_OUT),
|
| 446 |
|
|
.RXNOTINTABLE (RXNOTINTABLE_OUT),
|
| 447 |
|
|
.RXRUNDISP (),
|
| 448 |
|
|
.USRCODEERR (tied_to_ground_i),
|
| 449 |
|
|
//----------------- Receive Ports - Channel Bonding Ports ------------------
|
| 450 |
|
|
.RXCHANBONDSEQ (),
|
| 451 |
|
|
.RXCHBONDI (tied_to_ground_vec_i[3:0]),
|
| 452 |
|
|
.RXCHBONDLEVEL (tied_to_ground_vec_i[2:0]),
|
| 453 |
|
|
.RXCHBONDMASTER (tied_to_ground_i),
|
| 454 |
|
|
.RXCHBONDO (),
|
| 455 |
|
|
.RXCHBONDSLAVE (tied_to_ground_i),
|
| 456 |
|
|
.RXENCHANSYNC (tied_to_ground_i),
|
| 457 |
|
|
//----------------- Receive Ports - Clock Correction Ports -----------------
|
| 458 |
|
|
.RXCLKCORCNT (RXCLKCORCNT_OUT),
|
| 459 |
|
|
//------------- Receive Ports - Comma Detection and Alignment --------------
|
| 460 |
|
|
.RXBYTEISALIGNED (RXBYTEISALIGNED_OUT),
|
| 461 |
|
|
.RXBYTEREALIGN (RXBYTEREALIGN_OUT),
|
| 462 |
|
|
.RXCOMMADET (),
|
| 463 |
|
|
.RXCOMMADETUSE (tied_to_vcc_i),
|
| 464 |
|
|
.RXENMCOMMAALIGN (RXENMCOMMAALIGN_IN),
|
| 465 |
|
|
.RXENPCOMMAALIGN (RXENPCOMMAALIGN_IN),
|
| 466 |
|
|
.RXSLIDE (tied_to_ground_i),
|
| 467 |
|
|
//--------------------- Receive Ports - PRBS Detection ---------------------
|
| 468 |
|
|
.PRBSCNTRESET (tied_to_ground_i),
|
| 469 |
|
|
.RXENPRBSTST (tied_to_ground_vec_i[2:0]),
|
| 470 |
|
|
.RXPRBSERR (),
|
| 471 |
|
|
//----------------- Receive Ports - RX Data Path interface -----------------
|
| 472 |
|
|
.RXDATA (rxdata_i),
|
| 473 |
|
|
.RXRECCLK (RXRECCLK_OUT),
|
| 474 |
|
|
.RXRECCLKPCS (),
|
| 475 |
|
|
.RXRESET (RXRESET_IN),
|
| 476 |
|
|
.RXUSRCLK (RXUSRCLK_IN),
|
| 477 |
|
|
.RXUSRCLK2 (RXUSRCLK2_IN),
|
| 478 |
|
|
//---------- Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
|
| 479 |
|
|
.DFECLKDLYADJ (tied_to_ground_vec_i[5:0]),
|
| 480 |
|
|
.DFECLKDLYADJMON (),
|
| 481 |
|
|
.DFEDLYOVRD (tied_to_vcc_i),
|
| 482 |
|
|
.DFEEYEDACMON (),
|
| 483 |
|
|
.DFESENSCAL (),
|
| 484 |
|
|
.DFETAP1 (tied_to_ground_vec_i[4:0]),
|
| 485 |
|
|
.DFETAP1MONITOR (),
|
| 486 |
|
|
.DFETAP2 (tied_to_ground_vec_i[4:0]),
|
| 487 |
|
|
.DFETAP2MONITOR (),
|
| 488 |
|
|
.DFETAP3 (tied_to_ground_vec_i[3:0]),
|
| 489 |
|
|
.DFETAP3MONITOR (),
|
| 490 |
|
|
.DFETAP4 (tied_to_ground_vec_i[3:0]),
|
| 491 |
|
|
.DFETAP4MONITOR (),
|
| 492 |
|
|
.DFETAPOVRD (tied_to_vcc_i),
|
| 493 |
|
|
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
|
| 494 |
|
|
.GATERXELECIDLE (tied_to_ground_i),
|
| 495 |
|
|
.IGNORESIGDET (tied_to_ground_i),
|
| 496 |
|
|
.RXCDRRESET (RXBUFRESET_IN),
|
| 497 |
|
|
.RXELECIDLE (RXELECIDLE_OUT),
|
| 498 |
|
|
.RXEQMIX ({tied_to_ground_vec_i[6:0],RXEQMIX_IN}),
|
| 499 |
|
|
.RXN (RXN_IN),
|
| 500 |
|
|
.RXP (RXP_IN),
|
| 501 |
|
|
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
|
| 502 |
|
|
.RXBUFRESET (RXBUFRESET_IN),
|
| 503 |
|
|
.RXBUFSTATUS (),
|
| 504 |
|
|
.RXCHANISALIGNED (),
|
| 505 |
|
|
.RXCHANREALIGN (),
|
| 506 |
|
|
.RXDLYALIGNDISABLE (tied_to_ground_i),
|
| 507 |
|
|
.RXDLYALIGNMONENB (tied_to_ground_i),
|
| 508 |
|
|
.RXDLYALIGNMONITOR (),
|
| 509 |
|
|
.RXDLYALIGNOVERRIDE (tied_to_vcc_i),
|
| 510 |
|
|
.RXDLYALIGNRESET (tied_to_ground_i),
|
| 511 |
|
|
.RXDLYALIGNSWPPRECURB (tied_to_vcc_i),
|
| 512 |
|
|
.RXDLYALIGNUPDSW (tied_to_ground_i),
|
| 513 |
|
|
.RXENPMAPHASEALIGN (tied_to_ground_i),
|
| 514 |
|
|
.RXPMASETPHASE (tied_to_ground_i),
|
| 515 |
|
|
.RXSTATUS (RXSTATUS_OUT),
|
| 516 |
|
|
//------------- Receive Ports - RX Loss-of-sync State Machine --------------
|
| 517 |
|
|
.RXLOSSOFSYNC (),
|
| 518 |
|
|
//-------------------- Receive Ports - RX Oversampling ---------------------
|
| 519 |
|
|
.RXENSAMPLEALIGN (tied_to_ground_i),
|
| 520 |
|
|
.RXOVERSAMPLEERR (),
|
| 521 |
|
|
//---------------------- Receive Ports - RX PLL Ports ----------------------
|
| 522 |
|
|
.GREFCLKRX (tied_to_ground_i),
|
| 523 |
|
|
.GTXRXRESET (GTXRXRESET_IN),
|
| 524 |
|
|
.MGTREFCLKRX (MGTREFCLKRX_IN),
|
| 525 |
|
|
.NORTHREFCLKRX (tied_to_ground_vec_i[1:0]),
|
| 526 |
|
|
.PERFCLKRX (tied_to_ground_i),
|
| 527 |
|
|
.PLLRXRESET (PLLRXRESET_IN),
|
| 528 |
|
|
.RXPLLLKDET (RXPLLLKDET_OUT),
|
| 529 |
|
|
.RXPLLLKDETEN (tied_to_vcc_i),
|
| 530 |
|
|
.RXPLLPOWERDOWN (tied_to_ground_i),
|
| 531 |
|
|
.RXPLLREFSELDY (tied_to_ground_vec_i[2:0]),
|
| 532 |
|
|
.RXRATE (tied_to_ground_vec_i[1:0]),
|
| 533 |
|
|
.RXRATEDONE (),
|
| 534 |
|
|
.RXRESETDONE (RXRESETDONE_OUT),
|
| 535 |
|
|
.SOUTHREFCLKRX (tied_to_ground_vec_i[1:0]),
|
| 536 |
|
|
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
|
| 537 |
|
|
.PHYSTATUS (),
|
| 538 |
|
|
.RXVALID (),
|
| 539 |
|
|
//--------------- Receive Ports - RX Polarity Control Ports ----------------
|
| 540 |
|
|
.RXPOLARITY (tied_to_ground_i),
|
| 541 |
|
|
//------------------- Receive Ports - RX Ports for SATA --------------------
|
| 542 |
|
|
.COMINITDET (COMINITDET_OUT),
|
| 543 |
|
|
.COMSASDET (),
|
| 544 |
|
|
.COMWAKEDET (COMWAKEDET_OUT),
|
| 545 |
|
|
//----------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
|
| 546 |
|
|
.DADDR (DADDR),
|
| 547 |
|
|
.DCLK (DCLK),
|
| 548 |
|
|
.DEN (DEN),
|
| 549 |
|
|
.DI (DI),
|
| 550 |
|
|
.DRDY (DRDY),
|
| 551 |
|
|
.DRPDO (DO),
|
| 552 |
|
|
.DWE (DWE),
|
| 553 |
|
|
//------------ Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
|
| 554 |
|
|
.TXGEARBOXREADY (),
|
| 555 |
|
|
.TXHEADER (tied_to_ground_vec_i[2:0]),
|
| 556 |
|
|
.TXSEQUENCE (tied_to_ground_vec_i[6:0]),
|
| 557 |
|
|
.TXSTARTSEQ (tied_to_ground_i),
|
| 558 |
|
|
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
|
| 559 |
|
|
.TXBYPASS8B10B (tied_to_ground_vec_i[3:0]),
|
| 560 |
|
|
.TXCHARDISPMODE (tied_to_ground_vec_i[3:0]),
|
| 561 |
|
|
.TXCHARDISPVAL (tied_to_ground_vec_i[3:0]),
|
| 562 |
|
|
.TXCHARISK (TXCHARISK_IN),
|
| 563 |
|
|
.TXENC8B10BUSE (tied_to_vcc_i),
|
| 564 |
|
|
.TXKERR (),
|
| 565 |
|
|
.TXRUNDISP (),
|
| 566 |
|
|
//----------------------- Transmit Ports - GTX Ports -----------------------
|
| 567 |
|
|
.GTXTEST (13'b1000000000000),
|
| 568 |
|
|
.MGTREFCLKFAB (),
|
| 569 |
|
|
.TSTCLK0 (tied_to_ground_i),
|
| 570 |
|
|
.TSTCLK1 (tied_to_ground_i),
|
| 571 |
|
|
.TSTIN (20'b11111111111111111111),
|
| 572 |
|
|
.TSTOUT (),
|
| 573 |
|
|
//---------------- Transmit Ports - TX Data Path interface -----------------
|
| 574 |
|
|
.TXDATA (txdata_i),
|
| 575 |
|
|
.TXOUTCLK (TXOUTCLK_OUT),
|
| 576 |
|
|
.TXOUTCLKPCS (),
|
| 577 |
|
|
.TXRESET (TXRESET_IN),
|
| 578 |
|
|
.TXUSRCLK (TXUSRCLK_IN),
|
| 579 |
|
|
.TXUSRCLK2 (TXUSRCLK2_IN),
|
| 580 |
|
|
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
|
| 581 |
|
|
.TXBUFDIFFCTRL (3'b100),
|
| 582 |
|
|
.TXDIFFCTRL (TXDIFFCTRL_IN),
|
| 583 |
|
|
.TXINHIBIT (tied_to_ground_i),
|
| 584 |
|
|
.TXN (TXN_OUT),
|
| 585 |
|
|
.TXP (TXP_OUT),
|
| 586 |
|
|
.TXPOSTEMPHASIS (TXPOSTEMPHASIS_IN),
|
| 587 |
|
|
//------------- Transmit Ports - TX Driver and OOB signalling --------------
|
| 588 |
|
|
.TXPREEMPHASIS (TXPREEMPHASIS_IN),
|
| 589 |
|
|
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
|
| 590 |
|
|
.TXBUFSTATUS (),
|
| 591 |
|
|
//------ Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
|
| 592 |
|
|
.TXDLYALIGNDISABLE (tied_to_vcc_i),
|
| 593 |
|
|
.TXDLYALIGNMONENB (tied_to_ground_i),
|
| 594 |
|
|
.TXDLYALIGNMONITOR (),
|
| 595 |
|
|
.TXDLYALIGNOVERRIDE (tied_to_ground_i),
|
| 596 |
|
|
.TXDLYALIGNRESET (tied_to_ground_i),
|
| 597 |
|
|
.TXDLYALIGNUPDSW (tied_to_vcc_i),
|
| 598 |
|
|
.TXENPMAPHASEALIGN (tied_to_ground_i),
|
| 599 |
|
|
.TXPMASETPHASE (tied_to_ground_i),
|
| 600 |
|
|
//--------------------- Transmit Ports - TX PLL Ports ----------------------
|
| 601 |
|
|
.GREFCLKTX (tied_to_ground_i),
|
| 602 |
|
|
.GTXTXRESET (GTXTXRESET_IN),
|
| 603 |
|
|
.MGTREFCLKTX (MGTREFCLKTX_IN),
|
| 604 |
|
|
.NORTHREFCLKTX (tied_to_ground_vec_i[1:0]),
|
| 605 |
|
|
.PERFCLKTX (tied_to_ground_i),
|
| 606 |
|
|
.PLLTXRESET (PLLTXRESET_IN),
|
| 607 |
|
|
.SOUTHREFCLKTX (tied_to_ground_vec_i[1:0]),
|
| 608 |
|
|
.TXPLLLKDET (TXPLLLKDET_OUT),
|
| 609 |
|
|
.TXPLLLKDETEN (tied_to_vcc_i),
|
| 610 |
|
|
.TXPLLPOWERDOWN (tied_to_ground_i),
|
| 611 |
|
|
.TXPLLREFSELDY (tied_to_ground_vec_i[2:0]),
|
| 612 |
|
|
.TXRATE (tied_to_ground_vec_i[1:0]),
|
| 613 |
|
|
.TXRATEDONE (),
|
| 614 |
|
|
.TXRESETDONE (TXRESETDONE_OUT),
|
| 615 |
|
|
//------------------- Transmit Ports - TX PRBS Generator -------------------
|
| 616 |
|
|
.TXENPRBSTST (tied_to_ground_vec_i[2:0]),
|
| 617 |
|
|
.TXPRBSFORCEERR (tied_to_ground_i),
|
| 618 |
|
|
//------------------ Transmit Ports - TX Polarity Control ------------------
|
| 619 |
|
|
.TXPOLARITY (tied_to_ground_i),
|
| 620 |
|
|
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
|
| 621 |
|
|
.TXDEEMPH (tied_to_ground_i),
|
| 622 |
|
|
.TXDETECTRX (tied_to_ground_i),
|
| 623 |
|
|
.TXELECIDLE (TXELECIDLE_IN),
|
| 624 |
|
|
.TXMARGIN (tied_to_ground_vec_i[2:0]),
|
| 625 |
|
|
.TXPDOWNASYNCH (tied_to_ground_i),
|
| 626 |
|
|
.TXSWING (tied_to_ground_i),
|
| 627 |
|
|
//------------------- Transmit Ports - TX Ports for SATA -------------------
|
| 628 |
|
|
.COMFINISH (COMFINISH_OUT),
|
| 629 |
|
|
.TXCOMINIT (TXCOMINIT_IN),
|
| 630 |
|
|
.TXCOMSAS (tied_to_ground_i),
|
| 631 |
|
|
.TXCOMWAKE (TXCOMWAKE_IN)
|
| 632 |
|
|
|
| 633 |
|
|
);
|
| 634 |
|
|
|
| 635 |
|
|
endmodule
|
| 636 |
|
|
|
| 637 |
|
|
|
