Subversion Repositories sata_controller_core

///////////////////////////////////////////////////////////////////////////////

//   ____  ____ 

//  /   /\/   /

// /___/  \  /    Vendor: Xilinx

// \   \   \/     Version : 1.8

//  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard

//  /   /         Filename : sata_gtx_dual.v

// /___/   /\     

// \   \  /  \ 

//  \___\/\___\

//

//

// Module SATA_GTX_DUAL (a GTX Wrapper)

// Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard

// 

// 

// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.

// 

// This file contains confidential and proprietary information

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`timescale 1ns / 1ps

//***************************** Entity Declaration ****************************

(* CORE_GENERATION_INFO = "SATA_PHY,v6_gtxwizard_v1_8,{protocol_file=sata2}" *)

module SATA_GTX_DUAL #

(

    // Simulation attributes

    parameter   WRAPPER_SIM_GTXRESET_SPEEDUP    = 0    // Set to 1 to speed up sim reset

)

(

    //_________________________________________________________________________

    //_________________________________________________________________________

    //GTX0  (X0Y4)

    //---------------------- Loopback and Powerdown Ports ----------------------

    input   [2:0]   GTX0_LOOPBACK_IN,

    //--------------------- Receive Ports - 8b10b Decoder ----------------------

    output  [3:0]   GTX0_RXCHARISK_OUT,

    output  [3:0]   GTX0_RXDISPERR_OUT,

    output  [3:0]   GTX0_RXNOTINTABLE_OUT,

    //----------------- Receive Ports - Clock Correction Ports -----------------

    output  [2:0]   GTX0_RXCLKCORCNT_OUT,

    //------------- Receive Ports - Comma Detection and Alignment --------------

    output          GTX0_RXBYTEISALIGNED_OUT,

    output          GTX0_RXBYTEREALIGN_OUT,

    input           GTX0_RXENMCOMMAALIGN_IN,

    input           GTX0_RXENPCOMMAALIGN_IN,

    //----------------- Receive Ports - RX Data Path interface -----------------

    output  [31:0]  GTX0_RXDATA_OUT,

    output          GTX0_RXRECCLK_OUT,

    input           GTX0_RXRESET_IN,

    input           GTX0_RXUSRCLK_IN,

    input           GTX0_RXUSRCLK2_IN,

    //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------

    output          GTX0_RXELECIDLE_OUT,

    input   [2:0]   GTX0_RXEQMIX_IN,

    input           GTX0_RXN_IN,

    input           GTX0_RXP_IN,

    //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------

    input           GTX0_RXBUFRESET_IN,

    output  [2:0]   GTX0_RXSTATUS_OUT,

    //---------------------- Receive Ports - RX PLL Ports ----------------------

    input           GTX0_GTXRXRESET_IN,

    input           GTX0_MGTREFCLKRX_IN,

    input           GTX0_PLLRXRESET_IN,

    output          GTX0_RXPLLLKDET_OUT,

    output          GTX0_RXRESETDONE_OUT,

    //------------------- Receive Ports - RX Ports for SATA --------------------

    output          GTX0_COMINITDET_OUT,

    output          GTX0_COMWAKEDET_OUT,

    // -------------- Speed Neg Module ports ------------------------

    input [6:0]    DADDR,       //DRP address                     

    input          DEN,         //DRP enable

    input [15:0]   DI,           //DRP data in

    output[15:0]   DO,           //DRP data out

    output         DRDY,        //DRP ready

    input          DWE,         //DRP write enable

    input          DCLK,

    //-------------- Transmit Ports - 8b10b Encoder Control Ports --------------

    input   [3:0]   GTX0_TXCHARISK_IN,

    //---------------- Transmit Ports - TX Data Path interface -----------------

    input   [31:0]  GTX0_TXDATA_IN,

    output          GTX0_TXOUTCLK_OUT,

    input           GTX0_TXRESET_IN,

    input           GTX0_TXUSRCLK_IN,

    input           GTX0_TXUSRCLK2_IN,

    //-------------- Transmit Ports - TX Driver and OOB signaling --------------

    input   [3:0]   GTX0_TXDIFFCTRL_IN,

    output          GTX0_TXN_OUT,

    output          GTX0_TXP_OUT,

    input   [4:0]   GTX0_TXPOSTEMPHASIS_IN,

    //------------- Transmit Ports - TX Driver and OOB signalling --------------

    input   [3:0]   GTX0_TXPREEMPHASIS_IN,

    //--------------------- Transmit Ports - TX PLL Ports ----------------------

    input           GTX0_GTXTXRESET_IN,

    output          GTX0_TXRESETDONE_OUT,

    //--------------- Transmit Ports - TX Ports for PCI Express ----------------

    input           GTX0_TXELECIDLE_IN,

    //------------------- Transmit Ports - TX Ports for SATA -------------------

    output          GTX0_COMFINISH_OUT,

    input           GTX0_TXCOMINIT_IN,

    input           GTX0_TXCOMWAKE_IN,

    //_________________________________________________________________________

    //_________________________________________________________________________

    //GTX1  (X0Y5)

    //---------------------- Loopback and Powerdown Ports ----------------------

    input   [2:0]   GTX1_LOOPBACK_IN,

    //--------------------- Receive Ports - 8b10b Decoder ----------------------

    output  [3:0]   GTX1_RXDISPERR_OUT,

    output  [3:0]   GTX1_RXNOTINTABLE_OUT,

    //----------------- Receive Ports - Clock Correction Ports -----------------

    output  [2:0]   GTX1_RXCLKCORCNT_OUT,

    //------------- Receive Ports - Comma Detection and Alignment --------------

    output          GTX1_RXBYTEISALIGNED_OUT,

    output          GTX1_RXBYTEREALIGN_OUT,

    input           GTX1_RXENMCOMMAALIGN_IN,

    input           GTX1_RXENPCOMMAALIGN_IN,

    //----------------- Receive Ports - RX Data Path interface -----------------

    output  [31:0]  GTX1_RXDATA_OUT,

    output          GTX1_RXRECCLK_OUT,

    input           GTX1_RXRESET_IN,

    input           GTX1_RXUSRCLK_IN,

    input           GTX1_RXUSRCLK2_IN,

    //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------

    output          GTX1_RXELECIDLE_OUT,

    input   [2:0]   GTX1_RXEQMIX_IN,

    input           GTX1_RXN_IN,

    input           GTX1_RXP_IN,

    //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------

    input           GTX1_RXBUFRESET_IN,

    output  [2:0]   GTX1_RXSTATUS_OUT,

    //---------------------- Receive Ports - RX PLL Ports ----------------------

    input           GTX1_GTXRXRESET_IN,

    input           GTX1_MGTREFCLKRX_IN,

    input           GTX1_PLLRXRESET_IN,

    output          GTX1_RXPLLLKDET_OUT,

    output          GTX1_RXRESETDONE_OUT,

    //------------------- Receive Ports - RX Ports for SATA --------------------

    output          GTX1_COMINITDET_OUT,

    output          GTX1_COMWAKEDET_OUT,

    //-------------- Transmit Ports - 8b10b Encoder Control Ports --------------

    input   [3:0]   GTX1_TXCHARISK_IN,

    //---------------- Transmit Ports - TX Data Path interface -----------------

    input   [31:0]  GTX1_TXDATA_IN,

    output          GTX1_TXOUTCLK_OUT,

    input           GTX1_TXRESET_IN,

    input           GTX1_TXUSRCLK_IN,

    input           GTX1_TXUSRCLK2_IN,

    //-------------- Transmit Ports - TX Driver and OOB signaling --------------

    input   [3:0]   GTX1_TXDIFFCTRL_IN,

    output          GTX1_TXN_OUT,

    output          GTX1_TXP_OUT,

    input   [4:0]   GTX1_TXPOSTEMPHASIS_IN,

    //------------- Transmit Ports - TX Driver and OOB signalling --------------

    input   [3:0]   GTX1_TXPREEMPHASIS_IN,

    //--------------------- Transmit Ports - TX PLL Ports ----------------------

    input           GTX1_GTXTXRESET_IN,

    output          GTX1_TXRESETDONE_OUT,

    //--------------- Transmit Ports - TX Ports for PCI Express ----------------

    input           GTX1_TXELECIDLE_IN,

    //------------------- Transmit Ports - TX Ports for SATA -------------------

    output          GTX1_COMFINISH_OUT,

    input           GTX1_TXCOMINIT_IN,

    input           GTX1_TXCOMWAKE_IN

);

//***************************** Wire Declarations *****************************

    // ground and vcc signals

    wire            tied_to_ground_i;

    wire    [63:0]  tied_to_ground_vec_i;

    wire            tied_to_vcc_i;

    wire    [63:0]  tied_to_vcc_vec_i;

//********************************* Main Body of Code**************************

    assign tied_to_ground_i             = 1'b0;

    assign tied_to_ground_vec_i         = 64'h0000000000000000;

    assign tied_to_vcc_i                = 1'b1;

    assign tied_to_vcc_vec_i            = 64'hffffffffffffffff;

//------------------------- GTX Instances  -------------------------------

    //_________________________________________________________________________

    //_________________________________________________________________________

    //GTX0  (X0Y4)

    SATA_GTX #

    (

        // Simulation attributes

        .GTX_SIM_GTXRESET_SPEEDUP   (WRAPPER_SIM_GTXRESET_SPEEDUP),

        // Share RX PLL parameter

        .GTX_TX_CLK_SOURCE           ("RXPLL"),

        // Save power parameter

        .GTX_POWER_SAVE              (10'b0000110100)

    )

    gtx0_sata_i

    (

        //---------------------- Loopback and Powerdown Ports ----------------------

        .LOOPBACK_IN                    (GTX0_LOOPBACK_IN),

        //--------------------- Receive Ports - 8b10b Decoder ----------------------

        .RXCHARISK_OUT                  (GTX0_RXCHARISK_OUT),

        .RXDISPERR_OUT                  (GTX0_RXDISPERR_OUT),

        .RXNOTINTABLE_OUT               (GTX0_RXNOTINTABLE_OUT),

        //----------------- Receive Ports - Clock Correction Ports -----------------

        .RXCLKCORCNT_OUT                (GTX0_RXCLKCORCNT_OUT),

        //------------- Receive Ports - Comma Detection and Alignment --------------

        .RXBYTEISALIGNED_OUT            (GTX0_RXBYTEISALIGNED_OUT),

        .RXBYTEREALIGN_OUT              (GTX0_RXBYTEREALIGN_OUT),

        .RXENMCOMMAALIGN_IN             (GTX0_RXENMCOMMAALIGN_IN),

        .RXENPCOMMAALIGN_IN             (GTX0_RXENPCOMMAALIGN_IN),

        //----------------- Receive Ports - RX Data Path interface -----------------

        .RXDATA_OUT                     (GTX0_RXDATA_OUT),

        .RXRECCLK_OUT                   (GTX0_RXRECCLK_OUT),

        .RXRESET_IN                     (GTX0_RXRESET_IN),

        .RXUSRCLK_IN                    (GTX0_RXUSRCLK_IN),

        .RXUSRCLK2_IN                   (GTX0_RXUSRCLK2_IN),

        //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------

        .RXELECIDLE_OUT                 (GTX0_RXELECIDLE_OUT),

        .RXEQMIX_IN                     (GTX0_RXEQMIX_IN),

        .RXN_IN                         (GTX0_RXN_IN),

        .RXP_IN                         (GTX0_RXP_IN),

        //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------

        .RXBUFRESET_IN                  (GTX0_RXBUFRESET_IN),

        .RXSTATUS_OUT                   (GTX0_RXSTATUS_OUT),

        //---------------------- Receive Ports - RX PLL Ports ----------------------

        .GTXRXRESET_IN                  (GTX0_GTXRXRESET_IN),

        .MGTREFCLKRX_IN                 ({tied_to_ground_i , GTX0_MGTREFCLKRX_IN}),

        .PLLRXRESET_IN                  (GTX0_PLLRXRESET_IN),

        .RXPLLLKDET_OUT                 (GTX0_RXPLLLKDET_OUT),

        .RXRESETDONE_OUT                (GTX0_RXRESETDONE_OUT),

        //------------------- Receive Ports - RX Ports for SATA --------------------

        .COMINITDET_OUT                 (GTX0_COMINITDET_OUT),

        .COMWAKEDET_OUT                 (GTX0_COMWAKEDET_OUT),

        //----------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------

        .DADDR                          (DADDR),

        .DCLK                           (DCLK),

        .DEN                            (DEN),

        .DI                             (DI),

        .DRDY                           (DRDY),

        .DO                             (DO),

        .DWE                            (DWE),

        //-------------- Transmit Ports - 8b10b Encoder Control Ports --------------

        .TXCHARISK_IN                   (GTX0_TXCHARISK_IN),

        //---------------- Transmit Ports - TX Data Path interface -----------------

        .TXDATA_IN                      (GTX0_TXDATA_IN),

        .TXOUTCLK_OUT                   (GTX0_TXOUTCLK_OUT),

        .TXRESET_IN                     (GTX0_TXRESET_IN),

        .TXUSRCLK_IN                    (GTX0_TXUSRCLK_IN),

        .TXUSRCLK2_IN                   (GTX0_TXUSRCLK2_IN),

        //-------------- Transmit Ports - TX Driver and OOB signaling --------------

        .TXDIFFCTRL_IN                  (GTX0_TXDIFFCTRL_IN),

        .TXN_OUT                        (GTX0_TXN_OUT),

        .TXP_OUT                        (GTX0_TXP_OUT),

        .TXPOSTEMPHASIS_IN              (GTX0_TXPOSTEMPHASIS_IN),

        //------------- Transmit Ports - TX Driver and OOB signalling --------------

        .TXPREEMPHASIS_IN               (GTX0_TXPREEMPHASIS_IN),

        //--------------------- Transmit Ports - TX PLL Ports ----------------------

        .GTXTXRESET_IN                  (GTX0_GTXTXRESET_IN),

        .MGTREFCLKTX_IN                 ({tied_to_ground_i , GTX0_MGTREFCLKRX_IN}),

        .PLLTXRESET_IN                  (tied_to_ground_i),

        .TXPLLLKDET_OUT                 (),

        .TXRESETDONE_OUT                (GTX0_TXRESETDONE_OUT),

        //--------------- Transmit Ports - TX Ports for PCI Express ----------------

        .TXELECIDLE_IN                  (GTX0_TXELECIDLE_IN),

        //------------------- Transmit Ports - TX Ports for SATA -------------------

        .COMFINISH_OUT                  (GTX0_COMFINISH_OUT),

        .TXCOMINIT_IN                   (GTX0_TXCOMINIT_IN),

        .TXCOMWAKE_IN                   (GTX0_TXCOMWAKE_IN)

    );

    //_________________________________________________________________________

    //_________________________________________________________________________

    //GTX1  (X0Y5)

    SATA_GTX #

    (

        // Simulation attributes

        .GTX_SIM_GTXRESET_SPEEDUP   (WRAPPER_SIM_GTXRESET_SPEEDUP),

        // Share RX PLL parameter

        .GTX_TX_CLK_SOURCE           ("RXPLL"),

        // Save power parameter

        .GTX_POWER_SAVE              (10'b0000110100)

    )

    gtx1_sata_i

    (

        //---------------------- Loopback and Powerdown Ports ----------------------

        .LOOPBACK_IN                    (GTX1_LOOPBACK_IN),

        //--------------------- Receive Ports - 8b10b Decoder ----------------------

        .RXDISPERR_OUT                  (GTX1_RXDISPERR_OUT),

        .RXNOTINTABLE_OUT               (GTX1_RXNOTINTABLE_OUT),

        //----------------- Receive Ports - Clock Correction Ports -----------------

        .RXCLKCORCNT_OUT                (GTX1_RXCLKCORCNT_OUT),

        //------------- Receive Ports - Comma Detection and Alignment --------------

        .RXBYTEISALIGNED_OUT            (GTX1_RXBYTEISALIGNED_OUT),

        .RXBYTEREALIGN_OUT              (GTX1_RXBYTEREALIGN_OUT),

        .RXENMCOMMAALIGN_IN             (GTX1_RXENMCOMMAALIGN_IN),

        .RXENPCOMMAALIGN_IN             (GTX1_RXENPCOMMAALIGN_IN),

        //----------------- Receive Ports - RX Data Path interface -----------------

        .RXDATA_OUT                     (GTX1_RXDATA_OUT),

        .RXRECCLK_OUT                   (GTX1_RXRECCLK_OUT),

        .RXRESET_IN                     (GTX1_RXRESET_IN),

        .RXUSRCLK_IN                    (GTX1_RXUSRCLK_IN),

        .RXUSRCLK2_IN                   (GTX1_RXUSRCLK2_IN),

        //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------

        .RXELECIDLE_OUT                 (GTX1_RXELECIDLE_OUT),

        .RXEQMIX_IN                     (GTX1_RXEQMIX_IN),

        .RXN_IN                         (GTX1_RXN_IN),

        .RXP_IN                         (GTX1_RXP_IN),

        //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------

        .RXBUFRESET_IN                  (GTX1_RXBUFRESET_IN),

        .RXSTATUS_OUT                   (GTX1_RXSTATUS_OUT),

        //---------------------- Receive Ports - RX PLL Ports ----------------------

        .GTXRXRESET_IN                  (GTX1_GTXRXRESET_IN),

        .MGTREFCLKRX_IN                 ({tied_to_ground_i , GTX1_MGTREFCLKRX_IN}),

        .PLLRXRESET_IN                  (GTX1_PLLRXRESET_IN),

        .RXPLLLKDET_OUT                 (GTX1_RXPLLLKDET_OUT),

        .RXRESETDONE_OUT                (GTX1_RXRESETDONE_OUT),

        //------------------- Receive Ports - RX Ports for SATA --------------------

        .COMINITDET_OUT                 (GTX1_COMINITDET_OUT),

        .COMWAKEDET_OUT                 (GTX1_COMWAKEDET_OUT),

        //-------------- Transmit Ports - 8b10b Encoder Control Ports --------------

        .TXCHARISK_IN                   (GTX1_TXCHARISK_IN),

        //---------------- Transmit Ports - TX Data Path interface -----------------

        .TXDATA_IN                      (GTX1_TXDATA_IN),

        .TXOUTCLK_OUT                   (GTX1_TXOUTCLK_OUT),

        .TXRESET_IN                     (GTX1_TXRESET_IN),

        .TXUSRCLK_IN                    (GTX1_TXUSRCLK_IN),

        .TXUSRCLK2_IN                   (GTX1_TXUSRCLK2_IN),

        //-------------- Transmit Ports - TX Driver and OOB signaling --------------

        .TXDIFFCTRL_IN                  (GTX1_TXDIFFCTRL_IN),

        .TXN_OUT                        (GTX1_TXN_OUT),

        .TXP_OUT                        (GTX1_TXP_OUT),

        .TXPOSTEMPHASIS_IN              (GTX1_TXPOSTEMPHASIS_IN),

        //------------- Transmit Ports - TX Driver and OOB signalling --------------

        .TXPREEMPHASIS_IN               (GTX1_TXPREEMPHASIS_IN),

        //--------------------- Transmit Ports - TX PLL Ports ----------------------

        .GTXTXRESET_IN                  (GTX1_GTXTXRESET_IN),

        .MGTREFCLKTX_IN                 ({tied_to_ground_i , GTX1_MGTREFCLKRX_IN}),

        .PLLTXRESET_IN                  (tied_to_ground_i),

        .TXPLLLKDET_OUT                 (),

        .TXRESETDONE_OUT                (GTX1_TXRESETDONE_OUT),

        //--------------- Transmit Ports - TX Ports for PCI Express ----------------

        .TXELECIDLE_IN                  (GTX1_TXELECIDLE_IN),

        //------------------- Transmit Ports - TX Ports for SATA -------------------

        .COMFINISH_OUT                  (GTX1_COMFINISH_OUT),

        .TXCOMINIT_IN                   (GTX1_TXCOMINIT_IN),

        .TXCOMWAKE_IN                   (GTX1_TXCOMWAKE_IN)

    );

endmodule