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[/] [sata_controller_core/] [trunk/] [sata2_bus_v1_00_a/] [base_system/] [system_incl.make] - Blame information for rev 11

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Line No. Rev Author Line
1 11 ashwin_men
#################################################################
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# Makefile generated by Xilinx Platform Studio
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# Project:/raid/home/aamendon/open_source/svn/sata_controller_core/sata_controller_core/trunk/sata2_bus_v1_00_a/base_system/system.xmp
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#
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# WARNING : This file will be re-generated every time a command
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# to run a make target is invoked. So, any changes made to this
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# file manually, will be lost when make is invoked next.
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#################################################################
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XILINX_EDK_DIR = /raid/opt.x86_64/xilinx/12.2/ISE_DS/EDK
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NON_CYG_XILINX_EDK_DIR = /raid/opt.x86_64/xilinx/12.2/ISE_DS/EDK
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SYSTEM = system
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MHSFILE = system.mhs
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MSSFILE = system.mss
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FPGA_ARCH = virtex6
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DEVICE = xc6vlx240tff1156-1
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LANGUAGE = vhdl
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GLOBAL_SEARCHPATHOPT =
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PROJECT_SEARCHPATHOPT =
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SEARCHPATHOPT = $(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT)
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SUBMODULE_OPT =
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PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) -msg __xps/ise/xmsgprops.lst
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LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT) -msg __xps/ise/xmsgprops.lst \
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                   $(MICROBLAZE_0_LIBG_OPT)
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OBSERVE_PAR_OPTIONS = -error yes
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SATA_TEST_OUTPUT_DIR = sata_test
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SATA_TEST_OUTPUT = $(SATA_TEST_OUTPUT_DIR)/executable.elf
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CYG_SATA_TEST_OUTPUT_DIR = sata_test
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CYG_SATA_TEST_OUTPUT = $(CYG_SATA_TEST_OUTPUT_DIR)/executable.elf
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MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf
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PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf
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PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf
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BOOTLOOP_DIR = bootloops
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MICROBLAZE_0_BOOTLOOP = $(BOOTLOOP_DIR)/microblaze_0.elf
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MICROBLAZE_0_XMDSTUB = microblaze_0/code/xmdstub.elf
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BRAMINIT_ELF_FILES =  $(SATA_TEST_OUTPUT)
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BRAMINIT_ELF_FILE_ARGS =   -pe microblaze_0 $(SATA_TEST_OUTPUT)
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ALL_USER_ELF_FILES = $(SATA_TEST_OUTPUT)
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SIM_CMD = vsim
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BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM)_setup.do
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STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM)_setup.do
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TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.do
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DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)
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MIX_LANG_SIM_OPT = -mixed yes
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SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -s mti
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LIBRARIES =  \
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       microblaze_0/lib/libxil.a
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LIBSCLEAN_TARGETS = microblaze_0_libsclean
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PROGRAMCLEAN_TARGETS = sata_test_programclean
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CORE_STATE_DEVELOPMENT_FILES =
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WRAPPER_NGC_FILES = implementation/npi_core_0_wrapper.ngc \
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implementation/sata_core_0_wrapper.ngc \
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implementation/microblaze_0_wrapper.ngc \
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implementation/mb_plb_wrapper.ngc \
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implementation/ilmb_wrapper.ngc \
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implementation/dlmb_wrapper.ngc \
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implementation/dlmb_cntlr_wrapper.ngc \
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implementation/ilmb_cntlr_wrapper.ngc \
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implementation/lmb_bram_wrapper.ngc \
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implementation/rs232_uart_1_wrapper.ngc \
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implementation/ddr3_sdram_wrapper.ngc \
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implementation/clock_generator_0_wrapper.ngc \
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implementation/mdm_0_wrapper.ngc \
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implementation/proc_sys_reset_0_wrapper.ngc \
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implementation/chipscope_icon_0_wrapper.ngc
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POSTSYN_NETLIST = implementation/$(SYSTEM).ngc
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SYSTEM_BIT = implementation/$(SYSTEM).bit
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DOWNLOAD_BIT = implementation/download.bit
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SYSTEM_ACE = implementation/$(SYSTEM).ace
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UCF_FILE = data/system.ucf
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BMM_FILE = implementation/$(SYSTEM).bmm
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BITGEN_UT_FILE = etc/bitgen.ut
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XFLOW_OPT_FILE = etc/fast_runtime.opt
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XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE)
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XPLORER_DEPENDENCY = __xps/xplorer.opt
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XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7
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FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(XFLOW_DEPENDENCY)
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# cygwin path for windows
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SDK_EXPORT_DIR = SDK/SDK_Export/hw
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CYG_SDK_EXPORT_DIR = SDK/SDK_Export/hw
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SYSTEM_HW_HANDOFF = $(SDK_EXPORT_DIR)/$(SYSTEM).xml
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CYG_SYSTEM_HW_HANDOFF = $(CYG_SDK_EXPORT_DIR)/$(SYSTEM).xml
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SYSTEM_HW_HANDOFF_BIT = $(SDK_EXPORT_DIR)/$(SYSTEM).bit
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CYG_SYSTEM_HW_HANDOFF_BIT = $(CYG_SDK_EXPORT_DIR)/$(SYSTEM).bit
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SYSTEM_HW_HANDOFF_BMM = $(SDK_EXPORT_DIR)/$(SYSTEM)_bd.bmm
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CYG_SYSTEM_HW_HANDOFF_BMM = $(CYG_SDK_EXPORT_DIR)/$(SYSTEM)_bd.bmm
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SYSTEM_HW_HANDOFF_DEP = $(CYG_SYSTEM_HW_HANDOFF) $(CYG_SYSTEM_HW_HANDOFF_BIT) $(CYG_SYSTEM_HW_HANDOFF_BMM)
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#################################################################
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# SOFTWARE APPLICATION SATA_TEST
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#################################################################
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SATA_TEST_SOURCES = sata_test/sata_test.c
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SATA_TEST_HEADERS =
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SATA_TEST_CC = mb-gcc
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SATA_TEST_CC_SIZE = mb-size
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SATA_TEST_CC_OPT = -O2
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SATA_TEST_CFLAGS =
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SATA_TEST_CC_SEARCH = # -B
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SATA_TEST_LIBPATH = -L./microblaze_0/lib/ # -L
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SATA_TEST_INCLUDES = -I./microblaze_0/include/ # -I
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SATA_TEST_LFLAGS = # -l
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SATA_TEST_LINKER_SCRIPT =
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SATA_TEST_LINKER_SCRIPT_FLAG = #-T $(SATA_TEST_LINKER_SCRIPT)
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SATA_TEST_CC_DEBUG_FLAG =  -g
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SATA_TEST_CC_PROFILE_FLAG = # -pg
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SATA_TEST_CC_GLOBPTR_FLAG= # -mxl-gp-opt
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SATA_TEST_MODE = executable
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SATA_TEST_LIBG_OPT = -$(SATA_TEST_MODE) microblaze_0
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SATA_TEST_CC_INFERRED_FLAGS= -mno-xl-soft-mul -mxl-pattern-compare -mcpu=v7.30.b
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SATA_TEST_CC_START_ADDR_FLAG=  # -Wl,-defsym -Wl,_TEXT_START_ADDR=
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SATA_TEST_CC_STACK_SIZE_FLAG=  # -Wl,-defsym -Wl,_STACK_SIZE=
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SATA_TEST_CC_HEAP_SIZE_FLAG=  # -Wl,-defsym -Wl,_HEAP_SIZE=
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SATA_TEST_OTHER_CC_FLAGS= $(SATA_TEST_CC_GLOBPTR_FLAG)  \
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                  $(SATA_TEST_CC_START_ADDR_FLAG) $(SATA_TEST_CC_STACK_SIZE_FLAG) $(SATA_TEST_CC_HEAP_SIZE_FLAG)  \
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                  $(SATA_TEST_CC_INFERRED_FLAGS)  \
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                  $(SATA_TEST_LINKER_SCRIPT_FLAG) $(SATA_TEST_CC_DEBUG_FLAG) $(SATA_TEST_CC_PROFILE_FLAG)

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