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[/] [sata_controller_core/] [trunk/] [sata2_fifo_v1_00_a/] [hdl/] [verilog/] [mux_41.v] - Blame information for rev 13

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1 2 ashwin_men
//--------------------------------------------------------------------------------
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// Entity   mux_21 
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// Version: 1.0
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// Author:  Ashwin Mendon 
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// Description: 32 bit 4:1 Multiplexer
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//--------------------------------------------------------------------------------
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// Copyright (C) 2012
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// Ashwin A. Mendon
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//
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// This file is part of SATA2 core.
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.  
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module mux_41
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   (
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    input wire [31:0] a,
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    input wire [31:0] b,
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    input wire [31:0] c,
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    input wire [31:0] d,
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    input wire [1:0] sel,
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    output reg [31:0] o
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    );
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  always @ (a or b or c or d or sel)
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  begin
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    case (sel)
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      2'b00:
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          o = a;
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      2'b01:
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          o = b;
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      2'b10:
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          o = c;
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      2'b11:
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          o = d;
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     endcase
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  end
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endmodule
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