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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version : 1.8
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// \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard
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// / / Filename : sata_gtx_dual.v
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// /___/ /\
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// \ \ / \
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// \___\/\___\
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//
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//
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// Module SATA_GTX_DUAL (a GTX Wrapper)
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// Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
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//
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//
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// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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`timescale 1ns / 1ps
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//***************************** Entity Declaration ****************************
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(* CORE_GENERATION_INFO = "SATA_PHY,v6_gtxwizard_v1_8,{protocol_file=sata2}" *)
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module SATA_GTX_DUAL #
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(
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// Simulation attributes
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parameter WRAPPER_SIM_GTXRESET_SPEEDUP = 0 // Set to 1 to speed up sim reset
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)
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(
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//_________________________________________________________________________
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//_________________________________________________________________________
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//GTX0 (X0Y4)
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//---------------------- Loopback and Powerdown Ports ----------------------
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input [2:0] GTX0_LOOPBACK_IN,
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//--------------------- Receive Ports - 8b10b Decoder ----------------------
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output [3:0] GTX0_RXCHARISK_OUT,
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output [3:0] GTX0_RXDISPERR_OUT,
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output [3:0] GTX0_RXNOTINTABLE_OUT,
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//----------------- Receive Ports - Clock Correction Ports -----------------
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output [2:0] GTX0_RXCLKCORCNT_OUT,
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//------------- Receive Ports - Comma Detection and Alignment --------------
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output GTX0_RXBYTEISALIGNED_OUT,
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output GTX0_RXBYTEREALIGN_OUT,
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input GTX0_RXENMCOMMAALIGN_IN,
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input GTX0_RXENPCOMMAALIGN_IN,
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//----------------- Receive Ports - RX Data Path interface -----------------
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output [31:0] GTX0_RXDATA_OUT,
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output GTX0_RXRECCLK_OUT,
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input GTX0_RXRESET_IN,
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input GTX0_RXUSRCLK_IN,
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input GTX0_RXUSRCLK2_IN,
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//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
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output GTX0_RXELECIDLE_OUT,
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input [2:0] GTX0_RXEQMIX_IN,
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input GTX0_RXN_IN,
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input GTX0_RXP_IN,
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//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
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input GTX0_RXBUFRESET_IN,
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output [2:0] GTX0_RXSTATUS_OUT,
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//---------------------- Receive Ports - RX PLL Ports ----------------------
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input GTX0_GTXRXRESET_IN,
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input GTX0_MGTREFCLKRX_IN,
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input GTX0_PLLRXRESET_IN,
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output GTX0_RXPLLLKDET_OUT,
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output GTX0_RXRESETDONE_OUT,
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//------------------- Receive Ports - RX Ports for SATA --------------------
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output GTX0_COMINITDET_OUT,
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output GTX0_COMWAKEDET_OUT,
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// -------------- Speed Neg Module ports ------------------------
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input [6:0] DADDR, //DRP address
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input DEN, //DRP enable
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input [15:0] DI, //DRP data in
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output[15:0] DO, //DRP data out
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output DRDY, //DRP ready
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input DWE, //DRP write enable
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input DCLK,
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//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
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input [3:0] GTX0_TXCHARISK_IN,
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//---------------- Transmit Ports - TX Data Path interface -----------------
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input [31:0] GTX0_TXDATA_IN,
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output GTX0_TXOUTCLK_OUT,
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input GTX0_TXRESET_IN,
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input GTX0_TXUSRCLK_IN,
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input GTX0_TXUSRCLK2_IN,
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//-------------- Transmit Ports - TX Driver and OOB signaling --------------
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input [3:0] GTX0_TXDIFFCTRL_IN,
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output GTX0_TXN_OUT,
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output GTX0_TXP_OUT,
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input [4:0] GTX0_TXPOSTEMPHASIS_IN,
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//------------- Transmit Ports - TX Driver and OOB signalling --------------
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input [3:0] GTX0_TXPREEMPHASIS_IN,
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//--------------------- Transmit Ports - TX PLL Ports ----------------------
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input GTX0_GTXTXRESET_IN,
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output GTX0_TXRESETDONE_OUT,
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//--------------- Transmit Ports - TX Ports for PCI Express ----------------
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input GTX0_TXELECIDLE_IN,
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//------------------- Transmit Ports - TX Ports for SATA -------------------
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output GTX0_COMFINISH_OUT,
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input GTX0_TXCOMINIT_IN,
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input GTX0_TXCOMWAKE_IN,
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//_________________________________________________________________________
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//_________________________________________________________________________
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//GTX1 (X0Y5)
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//---------------------- Loopback and Powerdown Ports ----------------------
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input [2:0] GTX1_LOOPBACK_IN,
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//--------------------- Receive Ports - 8b10b Decoder ----------------------
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output [3:0] GTX1_RXDISPERR_OUT,
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output [3:0] GTX1_RXNOTINTABLE_OUT,
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//----------------- Receive Ports - Clock Correction Ports -----------------
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output [2:0] GTX1_RXCLKCORCNT_OUT,
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//------------- Receive Ports - Comma Detection and Alignment --------------
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output GTX1_RXBYTEISALIGNED_OUT,
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output GTX1_RXBYTEREALIGN_OUT,
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input GTX1_RXENMCOMMAALIGN_IN,
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input GTX1_RXENPCOMMAALIGN_IN,
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//----------------- Receive Ports - RX Data Path interface -----------------
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output [31:0] GTX1_RXDATA_OUT,
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output GTX1_RXRECCLK_OUT,
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input GTX1_RXRESET_IN,
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input GTX1_RXUSRCLK_IN,
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input GTX1_RXUSRCLK2_IN,
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//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
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output GTX1_RXELECIDLE_OUT,
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input [2:0] GTX1_RXEQMIX_IN,
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input GTX1_RXN_IN,
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input GTX1_RXP_IN,
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//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
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input GTX1_RXBUFRESET_IN,
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output [2:0] GTX1_RXSTATUS_OUT,
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//---------------------- Receive Ports - RX PLL Ports ----------------------
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input GTX1_GTXRXRESET_IN,
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input GTX1_MGTREFCLKRX_IN,
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input GTX1_PLLRXRESET_IN,
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output GTX1_RXPLLLKDET_OUT,
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output GTX1_RXRESETDONE_OUT,
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//------------------- Receive Ports - RX Ports for SATA --------------------
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output GTX1_COMINITDET_OUT,
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output GTX1_COMWAKEDET_OUT,
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//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
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input [3:0] GTX1_TXCHARISK_IN,
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//---------------- Transmit Ports - TX Data Path interface -----------------
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input [31:0] GTX1_TXDATA_IN,
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output GTX1_TXOUTCLK_OUT,
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input GTX1_TXRESET_IN,
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input GTX1_TXUSRCLK_IN,
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input GTX1_TXUSRCLK2_IN,
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//-------------- Transmit Ports - TX Driver and OOB signaling --------------
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input [3:0] GTX1_TXDIFFCTRL_IN,
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output GTX1_TXN_OUT,
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output GTX1_TXP_OUT,
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input [4:0] GTX1_TXPOSTEMPHASIS_IN,
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//------------- Transmit Ports - TX Driver and OOB signalling --------------
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input [3:0] GTX1_TXPREEMPHASIS_IN,
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//--------------------- Transmit Ports - TX PLL Ports ----------------------
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input GTX1_GTXTXRESET_IN,
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output GTX1_TXRESETDONE_OUT,
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//--------------- Transmit Ports - TX Ports for PCI Express ----------------
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input GTX1_TXELECIDLE_IN,
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//------------------- Transmit Ports - TX Ports for SATA -------------------
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output GTX1_COMFINISH_OUT,
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input GTX1_TXCOMINIT_IN,
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input GTX1_TXCOMWAKE_IN
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);
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//***************************** Wire Declarations *****************************
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// ground and vcc signals
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wire tied_to_ground_i;
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wire [63:0] tied_to_ground_vec_i;
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wire tied_to_vcc_i;
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wire [63:0] tied_to_vcc_vec_i;
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//********************************* Main Body of Code**************************
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assign tied_to_ground_i = 1'b0;
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assign tied_to_ground_vec_i = 64'h0000000000000000;
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assign tied_to_vcc_i = 1'b1;
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assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
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//------------------------- GTX Instances -------------------------------
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//_________________________________________________________________________
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//_________________________________________________________________________
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//GTX0 (X0Y4)
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SATA_GTX #
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(
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// Simulation attributes
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.GTX_SIM_GTXRESET_SPEEDUP (WRAPPER_SIM_GTXRESET_SPEEDUP),
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// Share RX PLL parameter
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.GTX_TX_CLK_SOURCE ("RXPLL"),
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// Save power parameter
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.GTX_POWER_SAVE (10'b0000110100)
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)
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gtx0_sata_i
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(
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//---------------------- Loopback and Powerdown Ports ----------------------
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.LOOPBACK_IN (GTX0_LOOPBACK_IN),
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//--------------------- Receive Ports - 8b10b Decoder ----------------------
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.RXCHARISK_OUT (GTX0_RXCHARISK_OUT),
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.RXDISPERR_OUT (GTX0_RXDISPERR_OUT),
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.RXNOTINTABLE_OUT (GTX0_RXNOTINTABLE_OUT),
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//----------------- Receive Ports - Clock Correction Ports -----------------
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.RXCLKCORCNT_OUT (GTX0_RXCLKCORCNT_OUT),
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//------------- Receive Ports - Comma Detection and Alignment --------------
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.RXBYTEISALIGNED_OUT (GTX0_RXBYTEISALIGNED_OUT),
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.RXBYTEREALIGN_OUT (GTX0_RXBYTEREALIGN_OUT),
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.RXENMCOMMAALIGN_IN (GTX0_RXENMCOMMAALIGN_IN),
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.RXENPCOMMAALIGN_IN (GTX0_RXENPCOMMAALIGN_IN),
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//----------------- Receive Ports - RX Data Path interface -----------------
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.RXDATA_OUT (GTX0_RXDATA_OUT),
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.RXRECCLK_OUT (GTX0_RXRECCLK_OUT),
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.RXRESET_IN (GTX0_RXRESET_IN),
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.RXUSRCLK_IN (GTX0_RXUSRCLK_IN),
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.RXUSRCLK2_IN (GTX0_RXUSRCLK2_IN),
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//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
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.RXELECIDLE_OUT (GTX0_RXELECIDLE_OUT),
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.RXEQMIX_IN (GTX0_RXEQMIX_IN),
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.RXN_IN (GTX0_RXN_IN),
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.RXP_IN (GTX0_RXP_IN),
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//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
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.RXBUFRESET_IN (GTX0_RXBUFRESET_IN),
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.RXSTATUS_OUT (GTX0_RXSTATUS_OUT),
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//---------------------- Receive Ports - RX PLL Ports ----------------------
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.GTXRXRESET_IN (GTX0_GTXRXRESET_IN),
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.MGTREFCLKRX_IN ({tied_to_ground_i , GTX0_MGTREFCLKRX_IN}),
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.PLLRXRESET_IN (GTX0_PLLRXRESET_IN),
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.RXPLLLKDET_OUT (GTX0_RXPLLLKDET_OUT),
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.RXRESETDONE_OUT (GTX0_RXRESETDONE_OUT),
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//------------------- Receive Ports - RX Ports for SATA --------------------
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.COMINITDET_OUT (GTX0_COMINITDET_OUT),
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.COMWAKEDET_OUT (GTX0_COMWAKEDET_OUT),
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//----------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
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.DADDR (DADDR),
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.DCLK (DCLK),
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.DEN (DEN),
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.DI (DI),
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.DRDY (DRDY),
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.DO (DO),
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.DWE (DWE),
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//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
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.TXCHARISK_IN (GTX0_TXCHARISK_IN),
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//---------------- Transmit Ports - TX Data Path interface -----------------
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.TXDATA_IN (GTX0_TXDATA_IN),
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.TXOUTCLK_OUT (GTX0_TXOUTCLK_OUT),
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.TXRESET_IN (GTX0_TXRESET_IN),
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.TXUSRCLK_IN (GTX0_TXUSRCLK_IN),
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.TXUSRCLK2_IN (GTX0_TXUSRCLK2_IN),
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//-------------- Transmit Ports - TX Driver and OOB signaling --------------
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.TXDIFFCTRL_IN (GTX0_TXDIFFCTRL_IN),
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.TXN_OUT (GTX0_TXN_OUT),
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|
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.TXP_OUT (GTX0_TXP_OUT),
|
312 |
|
|
.TXPOSTEMPHASIS_IN (GTX0_TXPOSTEMPHASIS_IN),
|
313 |
|
|
//------------- Transmit Ports - TX Driver and OOB signalling --------------
|
314 |
|
|
.TXPREEMPHASIS_IN (GTX0_TXPREEMPHASIS_IN),
|
315 |
|
|
//--------------------- Transmit Ports - TX PLL Ports ----------------------
|
316 |
|
|
.GTXTXRESET_IN (GTX0_GTXTXRESET_IN),
|
317 |
|
|
.MGTREFCLKTX_IN ({tied_to_ground_i , GTX0_MGTREFCLKRX_IN}),
|
318 |
|
|
.PLLTXRESET_IN (tied_to_ground_i),
|
319 |
|
|
.TXPLLLKDET_OUT (),
|
320 |
|
|
.TXRESETDONE_OUT (GTX0_TXRESETDONE_OUT),
|
321 |
|
|
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
|
322 |
|
|
.TXELECIDLE_IN (GTX0_TXELECIDLE_IN),
|
323 |
|
|
//------------------- Transmit Ports - TX Ports for SATA -------------------
|
324 |
|
|
.COMFINISH_OUT (GTX0_COMFINISH_OUT),
|
325 |
|
|
.TXCOMINIT_IN (GTX0_TXCOMINIT_IN),
|
326 |
|
|
.TXCOMWAKE_IN (GTX0_TXCOMWAKE_IN)
|
327 |
|
|
|
328 |
|
|
);
|
329 |
|
|
|
330 |
|
|
|
331 |
|
|
|
332 |
|
|
//_________________________________________________________________________
|
333 |
|
|
//_________________________________________________________________________
|
334 |
|
|
//GTX1 (X0Y5)
|
335 |
|
|
|
336 |
|
|
SATA_GTX #
|
337 |
|
|
(
|
338 |
|
|
// Simulation attributes
|
339 |
|
|
.GTX_SIM_GTXRESET_SPEEDUP (WRAPPER_SIM_GTXRESET_SPEEDUP),
|
340 |
|
|
|
341 |
|
|
// Share RX PLL parameter
|
342 |
|
|
.GTX_TX_CLK_SOURCE ("RXPLL"),
|
343 |
|
|
// Save power parameter
|
344 |
|
|
.GTX_POWER_SAVE (10'b0000110100)
|
345 |
|
|
)
|
346 |
|
|
gtx1_sata_i
|
347 |
|
|
(
|
348 |
|
|
//---------------------- Loopback and Powerdown Ports ----------------------
|
349 |
|
|
.LOOPBACK_IN (GTX1_LOOPBACK_IN),
|
350 |
|
|
//--------------------- Receive Ports - 8b10b Decoder ----------------------
|
351 |
|
|
.RXDISPERR_OUT (GTX1_RXDISPERR_OUT),
|
352 |
|
|
.RXNOTINTABLE_OUT (GTX1_RXNOTINTABLE_OUT),
|
353 |
|
|
//----------------- Receive Ports - Clock Correction Ports -----------------
|
354 |
|
|
.RXCLKCORCNT_OUT (GTX1_RXCLKCORCNT_OUT),
|
355 |
|
|
//------------- Receive Ports - Comma Detection and Alignment --------------
|
356 |
|
|
.RXBYTEISALIGNED_OUT (GTX1_RXBYTEISALIGNED_OUT),
|
357 |
|
|
.RXBYTEREALIGN_OUT (GTX1_RXBYTEREALIGN_OUT),
|
358 |
|
|
.RXENMCOMMAALIGN_IN (GTX1_RXENMCOMMAALIGN_IN),
|
359 |
|
|
.RXENPCOMMAALIGN_IN (GTX1_RXENPCOMMAALIGN_IN),
|
360 |
|
|
//----------------- Receive Ports - RX Data Path interface -----------------
|
361 |
|
|
.RXDATA_OUT (GTX1_RXDATA_OUT),
|
362 |
|
|
.RXRECCLK_OUT (GTX1_RXRECCLK_OUT),
|
363 |
|
|
.RXRESET_IN (GTX1_RXRESET_IN),
|
364 |
|
|
.RXUSRCLK_IN (GTX1_RXUSRCLK_IN),
|
365 |
|
|
.RXUSRCLK2_IN (GTX1_RXUSRCLK2_IN),
|
366 |
|
|
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
|
367 |
|
|
.RXELECIDLE_OUT (GTX1_RXELECIDLE_OUT),
|
368 |
|
|
.RXEQMIX_IN (GTX1_RXEQMIX_IN),
|
369 |
|
|
.RXN_IN (GTX1_RXN_IN),
|
370 |
|
|
.RXP_IN (GTX1_RXP_IN),
|
371 |
|
|
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
|
372 |
|
|
.RXBUFRESET_IN (GTX1_RXBUFRESET_IN),
|
373 |
|
|
.RXSTATUS_OUT (GTX1_RXSTATUS_OUT),
|
374 |
|
|
//---------------------- Receive Ports - RX PLL Ports ----------------------
|
375 |
|
|
.GTXRXRESET_IN (GTX1_GTXRXRESET_IN),
|
376 |
|
|
.MGTREFCLKRX_IN ({tied_to_ground_i , GTX1_MGTREFCLKRX_IN}),
|
377 |
|
|
.PLLRXRESET_IN (GTX1_PLLRXRESET_IN),
|
378 |
|
|
.RXPLLLKDET_OUT (GTX1_RXPLLLKDET_OUT),
|
379 |
|
|
.RXRESETDONE_OUT (GTX1_RXRESETDONE_OUT),
|
380 |
|
|
//------------------- Receive Ports - RX Ports for SATA --------------------
|
381 |
|
|
.COMINITDET_OUT (GTX1_COMINITDET_OUT),
|
382 |
|
|
.COMWAKEDET_OUT (GTX1_COMWAKEDET_OUT),
|
383 |
|
|
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
|
384 |
|
|
.TXCHARISK_IN (GTX1_TXCHARISK_IN),
|
385 |
|
|
//---------------- Transmit Ports - TX Data Path interface -----------------
|
386 |
|
|
.TXDATA_IN (GTX1_TXDATA_IN),
|
387 |
|
|
.TXOUTCLK_OUT (GTX1_TXOUTCLK_OUT),
|
388 |
|
|
.TXRESET_IN (GTX1_TXRESET_IN),
|
389 |
|
|
.TXUSRCLK_IN (GTX1_TXUSRCLK_IN),
|
390 |
|
|
.TXUSRCLK2_IN (GTX1_TXUSRCLK2_IN),
|
391 |
|
|
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
|
392 |
|
|
.TXDIFFCTRL_IN (GTX1_TXDIFFCTRL_IN),
|
393 |
|
|
.TXN_OUT (GTX1_TXN_OUT),
|
394 |
|
|
.TXP_OUT (GTX1_TXP_OUT),
|
395 |
|
|
.TXPOSTEMPHASIS_IN (GTX1_TXPOSTEMPHASIS_IN),
|
396 |
|
|
//------------- Transmit Ports - TX Driver and OOB signalling --------------
|
397 |
|
|
.TXPREEMPHASIS_IN (GTX1_TXPREEMPHASIS_IN),
|
398 |
|
|
//--------------------- Transmit Ports - TX PLL Ports ----------------------
|
399 |
|
|
.GTXTXRESET_IN (GTX1_GTXTXRESET_IN),
|
400 |
|
|
.MGTREFCLKTX_IN ({tied_to_ground_i , GTX1_MGTREFCLKRX_IN}),
|
401 |
|
|
.PLLTXRESET_IN (tied_to_ground_i),
|
402 |
|
|
.TXPLLLKDET_OUT (),
|
403 |
|
|
.TXRESETDONE_OUT (GTX1_TXRESETDONE_OUT),
|
404 |
|
|
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
|
405 |
|
|
.TXELECIDLE_IN (GTX1_TXELECIDLE_IN),
|
406 |
|
|
//------------------- Transmit Ports - TX Ports for SATA -------------------
|
407 |
|
|
.COMFINISH_OUT (GTX1_COMFINISH_OUT),
|
408 |
|
|
.TXCOMINIT_IN (GTX1_TXCOMINIT_IN),
|
409 |
|
|
.TXCOMWAKE_IN (GTX1_TXCOMWAKE_IN)
|
410 |
|
|
|
411 |
|
|
);
|
412 |
|
|
|
413 |
|
|
|
414 |
|
|
|
415 |
|
|
endmodule
|
416 |
|
|
|
417 |
|
|
|