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ashwin_men |
-- Copyright (C) 2012
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-- Ashwin A. Mendon
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--
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-- This file is part of SATA2 core.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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----------------------------------------------------------------------------------------
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-- ENTITY: sata_link_layer
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-- Version: 1.0
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-- Author: Ashwin Mendon
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-- Description: This sub-module implements the Transport and Link Layers of the SATA Protocol
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-- It is the heart of the SATA Core where the major functions of sending/receiving
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-- sequences of Frame Information Structures (FIS), packing them into
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-- Frames and sending/receiving Frames are accomplished.
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-- The Master FSM deals with the Transport Layer functions of sending receiving FISs
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-- using the TX and RX FSMs.
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-- The TX and RX FSMs use the crc, scrambler and primitive muxes to construct and
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-- deconstruct Frames. They also implement a Frame transmission/reception protocol.
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-- PORTS:
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-----------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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entity sata_link_layer is
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generic(
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CHIPSCOPE : boolean := false;
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DATA_WIDTH : natural := 32
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);
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port(
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-- Clock and Reset Signals
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--clk : in std_logic;
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sw_reset : in std_logic;
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-- ChipScope ILA / Trigger Signals
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sata_rx_frame_ila_control : in std_logic_vector(35 downto 0);
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sata_tx_frame_ila_control : in std_logic_vector(35 downto 0);
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--master_fsm_ila_control : in std_logic_vector(35 downto 0);
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oob_control_ila_control : in std_logic_vector(35 downto 0);
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sata_phy_ila_control : in std_logic_vector(35 downto 0);
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scrambler_ila_control : in std_logic_vector (35 downto 0);
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descrambler_ila_control : in std_logic_vector (35 downto 0);
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---------------------------------------
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-- Signals from/to User Logic
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sata_user_clk_out : out std_logic;
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GTX_RESET_IN : in std_logic;
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ready_for_cmd_out : out std_logic;
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new_cmd_in : in std_logic;
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cmd_type : in std_logic_vector(1 downto 0);
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sector_count : in integer;
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sata_din : in std_logic_vector(DATA_WIDTH-1 downto 0);
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sata_din_we : in std_logic;
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sata_dout : out std_logic_vector(DATA_WIDTH-1 downto 0);
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sata_dout_re : in std_logic;
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read_fifo_empty : out std_logic;
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write_fifo_full : out std_logic;
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---------------------------------------
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-- Ports from/to SATA PHY
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REFCLK_PAD_P_IN : in std_logic; -- MGTCLKA, clocks GTP_X0Y0-2
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REFCLK_PAD_N_IN : in std_logic; -- MGTCLKA
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TXP0_OUT : out std_logic;
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TXN0_OUT : out std_logic;
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RXP0_IN : in std_logic;
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RXN0_IN : in std_logic;
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PLLLKDET_OUT_N : out std_logic;
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DCMLOCKED_OUT : out std_logic;
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LINKUP_led : out std_logic;
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--GEN2_led : out std_logic;
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CLKIN_150 : in std_logic
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);
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end sata_link_layer;
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-------------------------------------------------------------------------------
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-- ARCHITECTURE
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-------------------------------------------------------------------------------
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architecture BEHAV of sata_link_layer is
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-------------------------------------------------------------------------------
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-- LINK LAYER
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Constants
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-------------------------------------------------------------------------------
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--Commands
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constant IDEN_DEV : std_logic_vector(1 downto 0) := "00";
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constant READ_DMA : std_logic_vector(1 downto 0) := "01";
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constant WRITE_DMA : std_logic_vector(1 downto 0) := "10";
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constant SET_FEATURES : std_logic_vector(1 downto 0) := "11";
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--Primitves
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constant SYNC : std_logic_vector(3 downto 0) := "0000";
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constant R_RDY : std_logic_vector(3 downto 0) := "0001";
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constant R_IP : std_logic_vector(3 downto 0) := "0010";
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constant R_OK : std_logic_vector(3 downto 0) := "0011";
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constant R_ERR : std_logic_vector(3 downto 0) := "0100";
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constant X_RDY : std_logic_vector(3 downto 0) := "0101";
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constant WTRM : std_logic_vector(3 downto 0) := "0110";
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constant HOLD : std_logic_vector(3 downto 0) := "0111";
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constant HOLD_ACK : std_logic_vector(3 downto 0) := "1000";
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constant CONT : std_logic_vector(3 downto 0) := "1001";
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constant SOF : std_logic_vector(3 downto 0) := "1010";
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constant EOF : std_logic_vector(3 downto 0) := "1011";
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constant FIS : std_logic_vector(3 downto 0) := "1100";
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constant PRIM_SCRM : std_logic_vector(3 downto 0) := "1101";
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constant COMMAND_FIS : std_logic_vector(15 downto 0) := conv_std_logic_vector(5, 16); -- (6DWORDS: 5 + 1CRC)
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--constant DATA_FIS : std_logic_vector(15 downto 0) := conv_std_logic_vector(259, 16); -- 260 WORDS (130DWORDS: 1FIS_TYPE + 128DATA + 1CRC)
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constant REG_FIS_NDWORDS : std_logic_vector(15 downto 0) := conv_std_logic_vector(6, 16); -- (6DWORDS: 5 + 1CRC)
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constant DATA_FIS_NDWORDS : integer := 130;
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constant SECTOR_NDWORDS : integer := 128; -- 256 WORDS / 512 Byte Sector
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constant NDWORDS_PER_DATA_FIS : std_logic_vector(15 downto 0) := conv_std_logic_vector(2048, 16);--128*16
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constant NDWORDS_PER_DATA_FIS_32 : std_logic_vector(31 downto 0) := conv_std_logic_vector(2048, 32);--128*16
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constant SYNC_COUNT_VALUE : std_logic_vector(7 downto 0) := conv_std_logic_vector(30, 8); -- 50 WORDS
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-----------------------------------------------------------------------------
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-- Finite State Machine Declaration (curr and next states)
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-----------------------------------------------------------------------------
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type MASTER_FSM_TYPE is (idle, capture_dev_sign, wait_for_cmd, H2D_REG_FIS, D2H_DMA_ACT_FIS,
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H2D_DATA_FIS, D2H_REG_FIS, D2H_DATA_FIS, D2H_PIO_SETUP, dead
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);
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signal master_fsm_curr, master_fsm_next : MASTER_FSM_TYPE := idle;
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signal master_fsm_value : std_logic_vector (0 to 3);
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type RX_FRAME_FSM_TYPE is (idle, send_R_RDY, send_R_IP, send_HOLD_ACK, send_R_OK,
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send_SYNC, wait_for_X_RDY, dead
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);
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signal rx_frame_curr, rx_frame_next : RX_FRAME_FSM_TYPE := idle;
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signal rx_frame_value : std_logic_vector (0 to 3);
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type TX_FRAME_FSM_TYPE is (idle, send_X_RDY, send_SOF, send_FIS, send_EOF, send_WTRM,
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send_SYNC, send_HOLD_ACK, send_HOLD, dead
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);
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signal tx_frame_curr, tx_frame_next : TX_FRAME_FSM_TYPE := idle;
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signal tx_frame_value : std_logic_vector (0 to 3);
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-----------------------------------------------------------------------------
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-- Finite State Machine Declaration (curr and next states)
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-----------------------------------------------------------------------------
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signal new_cmd : std_logic;
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signal FIS_word_count, FIS_word_count_next : std_logic_vector(0 to 15); --Counter for FIS WORD Count (WRITE)
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signal FIS_count_value, FIS_count_value_next : std_logic_vector(0 to 15); --Counter LIMIT for FIS WORD Count (WRITE)
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signal rx_sector_count : std_logic_vector(0 to 15); --Counter for number of received sectors
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signal tx_sector_count, tx_sector_count_next : std_logic_vector(0 to 15); --Counter for number of transmitted sectors
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signal dword_count : std_logic_vector(0 to 7); --Counter for DWORDS in each received sector
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signal DATA_FIS_dword_count : std_logic_vector(0 to 15); --Counter for DWORDS in each received DATA FIS
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signal dword_count_init_value : std_logic_vector(0 to 31);
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signal dword_count_value : std_logic_vector(0 to 15);
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signal start_rx, start_tx, rx_done, tx_done : std_logic;
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signal start_rx_next, start_tx_next, rx_done_next, tx_done_next : std_logic;
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signal prim_type_rx, prim_type_tx, prim_type : std_logic_vector (0 to 3);
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signal prim_type_rx_next, prim_type_tx_next : std_logic_vector (0 to 3);
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signal rx_tx_state_sel, rx_tx_state_sel_next : std_logic;
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signal sync_count_rx, sync_count_rx_next : std_logic_vector (0 to 7);
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signal sync_count_tx, sync_count_tx_next : std_logic_vector (0 to 7);
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signal ready_for_cmd_next : std_logic;
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signal ready_for_cmd : std_logic;
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signal frame_err, frame_err_next : std_logic;
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signal tx_err, tx_err_next : std_logic;
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signal tx_r_rdy, tx_r_ip, tx_r_ok, tx_r_err : std_logic_vector(0 to DATA_WIDTH-1);
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signal tx_x_rdy, tx_wtrm, tx_sof, tx_eof, tx_sync : std_logic_vector(0 to DATA_WIDTH-1);
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signal tx_hold, tx_hold_ack, tx_cont : std_logic_vector(0 to DATA_WIDTH-1);
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signal tx_dataout : std_logic_vector(0 to DATA_WIDTH-1);
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signal tx_charisk_out : std_logic;
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signal tx_charisk_RX_FRAME, tx_charisk_TX_FRAME: std_logic;
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signal output_mux_sel : std_logic_vector(0 to 3);
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signal align_en_out : std_logic;
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-- Primitive Detectors
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signal SYNC_det : std_logic;
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signal R_RDY_det : std_logic;
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signal R_IP_det : std_logic;
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signal R_OK_det : std_logic;
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signal R_ERR_det : std_logic;
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signal SOF_det : std_logic;
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signal EOF_det : std_logic;
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signal X_RDY_det : std_logic;
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signal WTRM_det : std_logic;
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signal CONT_det : std_logic;
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signal HOLD_det : std_logic;
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signal HOLD_det_r : std_logic;
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signal HOLD_det_r2 : std_logic;
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signal HOLD_det_r3 : std_logic;
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signal HOLD_det_r4 : std_logic;
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signal HOLD_start_det : std_logic;
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signal HOLD_stop_det : std_logic;
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signal HOLD_stop_after_ALIGN_det : std_logic;
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signal CORNER_CASE_HOLD : std_logic;
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signal HOLD_ACK_det : std_logic;
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signal ALIGN_det : std_logic;
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signal ALIGN_det_r : std_logic;
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signal ALIGN_det_r2 : std_logic;
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signal TWO_HOLD_det : std_logic;
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signal TWO_HOLD_det_r : std_logic;
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-----------------------------------------------------------------------------
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-- Internal Signals
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-----------------------------------------------------------------------------
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signal sata_user_clk : std_logic;
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signal rx_datain : std_logic_vector(0 to DATA_WIDTH-1);
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signal rxelecidle : std_logic;
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signal rx_charisk_in : std_logic_vector(3 downto 0);
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-- Debugging OOB
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signal OOB_state : std_logic_vector (0 to 7);
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signal LINKUP : std_logic;
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signal GEN2_led_i : std_logic;
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-- Scrambler/DeScrambler
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signal scrambler_din : std_logic_vector(0 to DATA_WIDTH-1);
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signal scrambler_dout : std_logic_vector(0 to DATA_WIDTH-1);
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signal scrambler_en, scrambler_en_r : std_logic;
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signal scrambler_din_re, scrambler_din_re_r : std_logic;
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signal scrambler_dout_we : std_logic;
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signal scrambler_reset : std_logic;
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signal scrambler_reset_after_FIS : std_logic;
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signal descrambler_din : std_logic_vector(0 to DATA_WIDTH-1);
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signal descrambler_dout : std_logic_vector(0 to DATA_WIDTH-1);
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signal descrambler_en : std_logic;
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signal descrambler_din_re, descrambler_din_re_r : std_logic;
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signal descrambler_dout_we : std_logic;
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signal descrambler_reset : std_logic;
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signal scrambler_count : std_logic_vector(0 to 15);
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signal scrambler_count_init_value : std_logic_vector(0 to 31);
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signal scrambler_count_value : std_logic_vector(0 to 15);
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signal scrambler_count_en_reg_fis : std_logic;
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signal scrambler_count_en_data_fis : std_logic;
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-- CRC
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signal crc_reset : std_logic;
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signal crc_din : std_logic_vector(0 to DATA_WIDTH-1);
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signal crc_dout : std_logic_vector(0 to DATA_WIDTH-1);
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signal crc_dout_r : std_logic_vector(0 to DATA_WIDTH-1);
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signal crc_en : std_logic;
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-----------------------------------------------------------------------------
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-- Post-DeScramble Read FIFO to Command Layer
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-----------------------------------------------------------------------------
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signal read_fifo_re : std_logic;
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signal read_fifo_we : std_logic;
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signal read_fifo_empty_i : std_logic;
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signal read_fifo_almost_empty : std_logic;
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signal read_fifo_full : std_logic;
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signal read_fifo_prog_full : std_logic;
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signal read_fifo_din : std_logic_vector(0 to DATA_WIDTH-1);
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signal read_fifo_dout : std_logic_vector(0 to DATA_WIDTH-1);
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-----------------------------------------------------------------------------
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-- Pre-DeScramble RX FIFO from PHY Layer
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-----------------------------------------------------------------------------
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signal rx_fifo_we : std_logic;
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signal rx_fifo_we_next : std_logic;
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signal rx_fifo_re : std_logic;
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signal rx_fifo_empty : std_logic;
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signal rx_fifo_almost_empty : std_logic;
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signal rx_fifo_full : std_logic;
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signal rx_fifo_prog_full : std_logic;
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signal rx_fifo_din : std_logic_vector(0 to DATA_WIDTH-1);
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signal rx_fifo_dout : std_logic_vector(0 to DATA_WIDTH-1);
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signal rx_fifo_data_count : std_logic_vector(0 to 9);
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-----------------------------------------------------------------------------
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-- Pre-Scramble Write FIFO from Command Layer
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-----------------------------------------------------------------------------
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signal write_fifo_we : std_logic;
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signal write_fifo_re : std_logic;
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signal write_fifo_empty : std_logic;
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signal write_fifo_almost_empty : std_logic;
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signal write_fifo_full_i : std_logic;
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signal write_fifo_prog_full : std_logic;
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signal write_fifo_din : std_logic_vector(0 to DATA_WIDTH-1);
|
289 |
|
|
signal write_fifo_dout : std_logic_vector(0 to DATA_WIDTH-1);
|
290 |
|
|
|
291 |
|
|
-----------------------------------------------------------------------------
|
292 |
|
|
-- Post-Scramble TX FIFO to PHY Layer
|
293 |
|
|
-----------------------------------------------------------------------------
|
294 |
|
|
signal tx_fifo_re : std_logic;
|
295 |
|
|
signal tx_fifo_re_next : std_logic;
|
296 |
|
|
signal tx_fifo_we : std_logic;
|
297 |
|
|
signal tx_fifo_empty : std_logic;
|
298 |
|
|
signal tx_fifo_almost_empty : std_logic;
|
299 |
|
|
signal tx_fifo_full : std_logic;
|
300 |
|
|
signal tx_fifo_prog_full : std_logic;
|
301 |
|
|
signal tx_fifo_din : std_logic_vector(0 to DATA_WIDTH-1);
|
302 |
|
|
signal tx_fifo_dout : std_logic_vector(0 to DATA_WIDTH-1);
|
303 |
|
|
signal tx_fifo_data_count : std_logic_vector(0 to 9);
|
304 |
|
|
|
305 |
|
|
-----------------------------------------------------------------------------
|
306 |
|
|
-- Replay FIFO Signals
|
307 |
|
|
-----------------------------------------------------------------------------
|
308 |
|
|
signal replay_buffer_clear : std_logic;
|
309 |
|
|
signal replay_buffer_clear_next: std_logic;
|
310 |
|
|
|
311 |
|
|
-----------------------------------------------------------------------------
|
312 |
|
|
-- FIFO Declarations
|
313 |
|
|
-----------------------------------------------------------------------------
|
314 |
|
|
component read_write_fifo
|
315 |
|
|
port (
|
316 |
|
|
clk: IN std_logic;
|
317 |
|
|
rst: IN std_logic;
|
318 |
|
|
rd_en: IN std_logic;
|
319 |
|
|
din: IN std_logic_VECTOR(31 downto 0);
|
320 |
|
|
wr_en: IN std_logic;
|
321 |
|
|
dout: OUT std_logic_VECTOR(31 downto 0);
|
322 |
|
|
almost_empty: OUT std_logic;
|
323 |
|
|
empty: OUT std_logic;
|
324 |
|
|
full: OUT std_logic;
|
325 |
|
|
prog_full: OUT std_logic
|
326 |
|
|
);
|
327 |
|
|
end component;
|
328 |
|
|
|
329 |
|
|
component rx_tx_fifo
|
330 |
|
|
port (
|
331 |
|
|
clk: IN std_logic;
|
332 |
|
|
rst: IN std_logic;
|
333 |
|
|
rd_en: IN std_logic;
|
334 |
|
|
din: IN std_logic_VECTOR(31 downto 0);
|
335 |
|
|
wr_en: IN std_logic;
|
336 |
|
|
dout: OUT std_logic_VECTOR(31 downto 0);
|
337 |
|
|
almost_empty: OUT std_logic;
|
338 |
|
|
empty: OUT std_logic;
|
339 |
|
|
full: OUT std_logic;
|
340 |
|
|
prog_full: OUT std_logic;
|
341 |
|
|
data_count: OUT std_logic_vector(9 downto 0)
|
342 |
|
|
);
|
343 |
|
|
end component;
|
344 |
|
|
|
345 |
|
|
-----------------------------------------------------------------------------
|
346 |
|
|
-- SATA PHY Declaration
|
347 |
|
|
-----------------------------------------------------------------------------
|
348 |
|
|
component sata_phy
|
349 |
|
|
port (
|
350 |
|
|
oob_control_ila_control: in std_logic_vector(35 downto 0);
|
351 |
|
|
sata_phy_ila_control : in std_logic_vector(35 downto 0);
|
352 |
|
|
REFCLK_PAD_P_IN : in std_logic; -- MGTCLKA, clocks GTP_X0Y0-2
|
353 |
|
|
REFCLK_PAD_N_IN : in std_logic; -- MGTCLKA
|
354 |
|
|
GTXRESET_IN : in std_logic; -- GTP initialization
|
355 |
|
|
PLLLKDET_OUT_N : out std_logic;
|
356 |
|
|
TXP0_OUT : out std_logic;
|
357 |
|
|
TXN0_OUT : out std_logic;
|
358 |
|
|
RXP0_IN : in std_logic;
|
359 |
|
|
RXN0_IN : in std_logic;
|
360 |
|
|
DCMLOCKED_OUT : out std_logic;
|
361 |
|
|
LINKUP : out std_logic;
|
362 |
|
|
LINKUP_led : out std_logic;
|
363 |
|
|
sata_user_clk : out std_logic;
|
364 |
|
|
GEN2_led : out std_logic;
|
365 |
|
|
align_en_out : out std_logic;
|
366 |
|
|
tx_datain : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
367 |
|
|
tx_charisk_in : in std_logic;
|
368 |
|
|
rx_dataout : out std_logic_vector(DATA_WIDTH-1 downto 0);
|
369 |
|
|
rx_charisk_out : out std_logic_vector(3 downto 0);
|
370 |
|
|
CurrentState_out : out std_logic_vector(7 downto 0);
|
371 |
|
|
rxelecidle_out : out std_logic;
|
372 |
|
|
CLKIN_150 : in std_logic
|
373 |
|
|
);
|
374 |
|
|
end component;
|
375 |
|
|
|
376 |
|
|
component sata_rx_frame_ila
|
377 |
|
|
port (
|
378 |
|
|
control : in std_logic_vector(35 downto 0);
|
379 |
|
|
clk : in std_logic;
|
380 |
|
|
trig0 : in std_logic_vector(3 downto 0);
|
381 |
|
|
trig1 : in std_logic_vector(31 downto 0);
|
382 |
|
|
trig2 : in std_logic_vector(7 downto 0);
|
383 |
|
|
trig3 : in std_logic_vector(3 downto 0);
|
384 |
|
|
trig4 : in std_logic_vector(3 downto 0);
|
385 |
|
|
trig5 : in std_logic_vector(7 downto 0);
|
386 |
|
|
trig6 : in std_logic_vector(31 downto 0);
|
387 |
|
|
trig7 : in std_logic_vector(31 downto 0);
|
388 |
|
|
trig8 : in std_logic_vector(31 downto 0);
|
389 |
|
|
trig9 : in std_logic_vector(31 downto 0);
|
390 |
|
|
trig10 : in std_logic_vector(31 downto 0);
|
391 |
|
|
trig11 : in std_logic_vector(7 downto 0);
|
392 |
|
|
trig12 : in std_logic_vector(15 downto 0);
|
393 |
|
|
trig13 : in std_logic_vector(15 downto 0);
|
394 |
|
|
trig14 : in std_logic_vector(15 downto 0);
|
395 |
|
|
trig15 : in std_logic_vector(31 downto 0)
|
396 |
|
|
);
|
397 |
|
|
end component;
|
398 |
|
|
|
399 |
|
|
|
400 |
|
|
component sata_tx_frame_ila
|
401 |
|
|
port (
|
402 |
|
|
control : in std_logic_vector(35 downto 0);
|
403 |
|
|
clk : in std_logic;
|
404 |
|
|
trig0 : in std_logic_vector(3 downto 0);
|
405 |
|
|
trig1 : in std_logic_vector(31 downto 0);
|
406 |
|
|
trig2 : in std_logic_vector(31 downto 0);
|
407 |
|
|
trig3 : in std_logic_vector(31 downto 0);
|
408 |
|
|
trig4 : in std_logic_vector(3 downto 0);
|
409 |
|
|
trig5 : in std_logic_vector(31 downto 0);
|
410 |
|
|
trig6 : in std_logic_vector(31 downto 0);
|
411 |
|
|
trig7 : in std_logic_vector(31 downto 0);
|
412 |
|
|
trig8 : in std_logic_vector(15 downto 0);
|
413 |
|
|
trig9 : in std_logic_vector(15 downto 0);
|
414 |
|
|
trig10 : in std_logic_vector(31 downto 0);
|
415 |
|
|
trig11 : in std_logic_vector(31 downto 0);
|
416 |
|
|
trig12 : in std_logic_vector(31 downto 0);
|
417 |
|
|
trig13 : in std_logic_vector(15 downto 0);
|
418 |
|
|
trig14 : in std_logic_vector(15 downto 0);
|
419 |
|
|
trig15 : in std_logic_vector(9 downto 0)
|
420 |
|
|
);
|
421 |
|
|
end component;
|
422 |
|
|
|
423 |
|
|
-------------------------------------------------------------------------------
|
424 |
|
|
-- BEGIN
|
425 |
|
|
-------------------------------------------------------------------------------
|
426 |
|
|
begin
|
427 |
|
|
|
428 |
|
|
-------------------------------------------------------------------------------
|
429 |
|
|
-- LINK LAYER
|
430 |
|
|
-------------------------------------------------------------------------------
|
431 |
|
|
|
432 |
|
|
-----------------------------------------------------------------------------
|
433 |
|
|
-- PROCESS: MASTER_FSM_VALUE_PROC
|
434 |
|
|
-- PURPOSE: ChipScope State Indicator Signal
|
435 |
|
|
-----------------------------------------------------------------------------
|
436 |
|
|
MASTER_FSM_VALUE_PROC : process (master_fsm_curr) is
|
437 |
|
|
begin
|
438 |
|
|
case (master_fsm_curr) is
|
439 |
|
|
when idle => master_fsm_value <= x"0";
|
440 |
|
|
when capture_dev_sign => master_fsm_value <= x"1";
|
441 |
|
|
when wait_for_cmd => master_fsm_value <= x"2";
|
442 |
|
|
when H2D_REG_FIS => master_fsm_value <= x"3";
|
443 |
|
|
when D2H_DMA_ACT_FIS => master_fsm_value <= x"4";
|
444 |
|
|
when H2D_DATA_FIS => master_fsm_value <= x"5";
|
445 |
|
|
when D2H_DATA_FIS => master_fsm_value <= x"6";
|
446 |
|
|
when D2H_REG_FIS => master_fsm_value <= x"7";
|
447 |
|
|
when D2H_PIO_SETUP => master_fsm_value <= x"8";
|
448 |
|
|
when dead => master_fsm_value <= x"9";
|
449 |
|
|
when others => master_fsm_value <= x"A";
|
450 |
|
|
end case;
|
451 |
|
|
end process MASTER_FSM_VALUE_PROC;
|
452 |
|
|
|
453 |
|
|
-----------------------------------------------------------------------------
|
454 |
|
|
-- PROCESS: MASTER_FSM_STATE_PROC
|
455 |
|
|
-- PURPOSE: Registering Signals and Next State
|
456 |
|
|
-----------------------------------------------------------------------------
|
457 |
|
|
MASTER_FSM_STATE_PROC : process (sata_user_clk)
|
458 |
|
|
begin
|
459 |
|
|
if ((sata_user_clk'event) and (sata_user_clk = '1')) then
|
460 |
|
|
if (sw_reset = '1') then
|
461 |
|
|
--Initializing internal signals
|
462 |
|
|
master_fsm_curr <= idle;
|
463 |
|
|
FIS_count_value <= (others => '0');
|
464 |
|
|
start_rx <= '0';
|
465 |
|
|
start_tx <= '0';
|
466 |
|
|
new_cmd <= '0';
|
467 |
|
|
ready_for_cmd <= '0';
|
468 |
|
|
else
|
469 |
|
|
-- Register all Current Signals to their _next Signals
|
470 |
|
|
master_fsm_curr <= master_fsm_next;
|
471 |
|
|
FIS_count_value <= FIS_count_value_next;
|
472 |
|
|
start_rx <= start_rx_next;
|
473 |
|
|
start_tx <= start_tx_next;
|
474 |
|
|
ready_for_cmd <= ready_for_cmd_next;
|
475 |
|
|
if (new_cmd_in = '1') then
|
476 |
|
|
new_cmd <= '1';
|
477 |
|
|
else
|
478 |
|
|
new_cmd <= '0';
|
479 |
|
|
end if;
|
480 |
|
|
end if;
|
481 |
|
|
end if;
|
482 |
|
|
end process MASTER_FSM_STATE_PROC;
|
483 |
|
|
|
484 |
|
|
-----------------------------------------------------------------------------
|
485 |
|
|
-- PROCESS: MASTER_FSM_LOGIC_PROC
|
486 |
|
|
-- PURPOSE: Implements a Sequence of FIS transfers for sending READ/WRITE sector
|
487 |
|
|
-- command. (Transport Layer)
|
488 |
|
|
-----------------------------------------------------------------------------
|
489 |
|
|
MASTER_FSM_LOGIC_PROC : process (master_fsm_curr, rx_done, tx_done, tx_err,
|
490 |
|
|
LINKUP, new_cmd, tx_sector_count
|
491 |
|
|
) is
|
492 |
|
|
begin
|
493 |
|
|
-- Register _next to current signals
|
494 |
|
|
master_fsm_next <= master_fsm_curr;
|
495 |
|
|
FIS_count_value_next <= (others => '0');
|
496 |
|
|
start_rx_next <= start_rx;
|
497 |
|
|
start_tx_next <= start_tx;
|
498 |
|
|
---------------------------------------------------------------------------
|
499 |
|
|
-- Finite State Machine
|
500 |
|
|
---------------------------------------------------------------------------
|
501 |
|
|
case (master_fsm_curr) is
|
502 |
|
|
|
503 |
|
|
-- x0
|
504 |
|
|
when idle =>
|
505 |
|
|
if (LINKUP = '1') then
|
506 |
|
|
start_rx_next <= '1';
|
507 |
|
|
master_fsm_next <= capture_dev_sign;
|
508 |
|
|
end if;
|
509 |
|
|
|
510 |
|
|
-- x1
|
511 |
|
|
when capture_dev_sign =>
|
512 |
|
|
start_rx_next <= '0';
|
513 |
|
|
if (rx_done = '1') then
|
514 |
|
|
master_fsm_next <= wait_for_cmd;
|
515 |
|
|
end if;
|
516 |
|
|
|
517 |
|
|
-- x2
|
518 |
|
|
when wait_for_cmd =>
|
519 |
|
|
if (new_cmd = '1') then
|
520 |
|
|
start_tx_next <= '1';
|
521 |
|
|
master_fsm_next <= H2D_REG_FIS;
|
522 |
|
|
end if;
|
523 |
|
|
|
524 |
|
|
-- x3
|
525 |
|
|
when H2D_REG_FIS =>
|
526 |
|
|
FIS_count_value_next <= COMMAND_FIS;
|
527 |
|
|
start_tx_next <= '0';
|
528 |
|
|
if (tx_done = '1') then
|
529 |
|
|
start_rx_next <= '1';
|
530 |
|
|
case (cmd_type) is
|
531 |
|
|
when IDEN_DEV =>
|
532 |
|
|
master_fsm_next <= D2H_PIO_SETUP;
|
533 |
|
|
when READ_DMA =>
|
534 |
|
|
master_fsm_next <= D2H_DATA_FIS;
|
535 |
|
|
when WRITE_DMA =>
|
536 |
|
|
master_fsm_next <= D2H_DMA_ACT_FIS;
|
537 |
|
|
when others =>
|
538 |
|
|
master_fsm_next <= D2H_REG_FIS;
|
539 |
|
|
end case;
|
540 |
|
|
end if;
|
541 |
|
|
if(tx_err = '1') then
|
542 |
|
|
start_tx_next <= '1';
|
543 |
|
|
master_fsm_next <= H2D_REG_FIS;
|
544 |
|
|
end if;
|
545 |
|
|
|
546 |
|
|
-- x4
|
547 |
|
|
when D2H_DMA_ACT_FIS =>
|
548 |
|
|
start_rx_next <= '0';
|
549 |
|
|
if (rx_done = '1') then
|
550 |
|
|
start_tx_next <= '1';
|
551 |
|
|
master_fsm_next <= H2D_DATA_FIS;
|
552 |
|
|
end if;
|
553 |
|
|
|
554 |
|
|
-- x5
|
555 |
|
|
when H2D_DATA_FIS =>
|
556 |
|
|
--FIS_count_value_next <= conv_std_logic_vector(((SECTOR_NDWORDS * sector_count) + 1), 16);
|
557 |
|
|
FIS_count_value_next <= (NDWORDS_PER_DATA_FIS + 1);
|
558 |
|
|
start_tx_next <= '0';
|
559 |
|
|
if ((tx_done = '1') or (tx_err = '1')) then
|
560 |
|
|
start_rx_next <= '1';
|
561 |
|
|
if (tx_sector_count >= conv_std_logic_vector(sector_count, 16)) then
|
562 |
|
|
master_fsm_next <= D2H_REG_FIS;
|
563 |
|
|
else
|
564 |
|
|
master_fsm_next <= D2H_DMA_ACT_FIS;
|
565 |
|
|
end if;
|
566 |
|
|
end if;
|
567 |
|
|
|
568 |
|
|
-- x6
|
569 |
|
|
when D2H_DATA_FIS =>
|
570 |
|
|
start_rx_next <= '0';
|
571 |
|
|
if (rx_done = '1') then
|
572 |
|
|
if (cmd_type = READ_DMA) then
|
573 |
|
|
start_rx_next <= '1';
|
574 |
|
|
master_fsm_next <= D2H_REG_FIS;
|
575 |
|
|
else
|
576 |
|
|
master_fsm_next <= wait_for_cmd;
|
577 |
|
|
end if;
|
578 |
|
|
end if;
|
579 |
|
|
|
580 |
|
|
-- x7
|
581 |
|
|
when D2H_REG_FIS =>
|
582 |
|
|
start_rx_next <= '0';
|
583 |
|
|
if (rx_done = '1') then
|
584 |
|
|
master_fsm_next <= wait_for_cmd;
|
585 |
|
|
end if;
|
586 |
|
|
|
587 |
|
|
-- x8
|
588 |
|
|
when D2H_PIO_SETUP =>
|
589 |
|
|
start_rx_next <= '0';
|
590 |
|
|
if (rx_done = '1') then
|
591 |
|
|
start_rx_next <= '1';
|
592 |
|
|
master_fsm_next <= D2H_DATA_FIS;
|
593 |
|
|
end if;
|
594 |
|
|
|
595 |
|
|
-- x9
|
596 |
|
|
when dead =>
|
597 |
|
|
master_fsm_next <= dead;
|
598 |
|
|
|
599 |
|
|
-- xA
|
600 |
|
|
when others =>
|
601 |
|
|
master_fsm_next <= dead;
|
602 |
|
|
|
603 |
|
|
end case;
|
604 |
|
|
end process MASTER_FSM_LOGIC_PROC;
|
605 |
|
|
|
606 |
|
|
ready_for_cmd_next <= '1' when (master_fsm_curr = wait_for_cmd) else '0';
|
607 |
|
|
ready_for_cmd_out <= ready_for_cmd;
|
608 |
|
|
|
609 |
|
|
-----------------------------------------------------------------------------
|
610 |
|
|
-- PROCESS: RX_FRAME_VALUE_PROC
|
611 |
|
|
-- PURPOSE: ChipScope State Indicator Signal
|
612 |
|
|
-----------------------------------------------------------------------------
|
613 |
|
|
RX_FRAME_VALUE_PROC : process (rx_frame_curr) is
|
614 |
|
|
begin
|
615 |
|
|
case (rx_frame_curr) is
|
616 |
|
|
when idle => rx_frame_value <= x"0";
|
617 |
|
|
when send_R_RDY => rx_frame_value <= x"1";
|
618 |
|
|
when send_R_IP => rx_frame_value <= x"2";
|
619 |
|
|
when send_HOLD_ACK => rx_frame_value <= x"3";
|
620 |
|
|
when send_R_OK => rx_frame_value <= x"4";
|
621 |
|
|
when send_SYNC => rx_frame_value <= x"5";
|
622 |
|
|
when wait_for_X_RDY => rx_frame_value <= x"6";
|
623 |
|
|
when dead => rx_frame_value <= x"7";
|
624 |
|
|
when others => rx_frame_value <= x"8";
|
625 |
|
|
end case;
|
626 |
|
|
end process RX_FRAME_VALUE_PROC;
|
627 |
|
|
|
628 |
|
|
-----------------------------------------------------------------------------
|
629 |
|
|
-- PROCESS: RX_FRAME_STATE_PROC
|
630 |
|
|
-- PURPOSE: Registering Signals and Next State
|
631 |
|
|
-----------------------------------------------------------------------------
|
632 |
|
|
RX_FRAME_STATE_PROC : process (sata_user_clk)
|
633 |
|
|
begin
|
634 |
|
|
if ((sata_user_clk'event) and (sata_user_clk = '1')) then
|
635 |
|
|
if (sw_reset = '1') then
|
636 |
|
|
--Initializing internal signals
|
637 |
|
|
rx_frame_curr <= idle;
|
638 |
|
|
sync_count_rx <= (others => '0');
|
639 |
|
|
rx_done <= '0';
|
640 |
|
|
rx_fifo_we <= '0';
|
641 |
|
|
prim_type_rx <= (others => '0');
|
642 |
|
|
ALIGN_det_r <= '0';
|
643 |
|
|
ALIGN_det_r2 <= '0';
|
644 |
|
|
HOLD_det_r <= '0';
|
645 |
|
|
HOLD_det_r2 <= '0';
|
646 |
|
|
HOLD_det_r3 <= '0';
|
647 |
|
|
HOLD_det_r4 <= '0';
|
648 |
|
|
TWO_HOLD_det_r <= '0';
|
649 |
|
|
else
|
650 |
|
|
-- Register all Current Signals to their _next Signals
|
651 |
|
|
rx_frame_curr <= rx_frame_next;
|
652 |
|
|
sync_count_rx <= sync_count_rx_next;
|
653 |
|
|
rx_done <= rx_done_next;
|
654 |
|
|
rx_fifo_we <= rx_fifo_we_next;
|
655 |
|
|
prim_type_rx <= prim_type_rx_next;
|
656 |
|
|
ALIGN_det_r <= ALIGN_det;
|
657 |
|
|
ALIGN_det_r2 <= ALIGN_det_r;
|
658 |
|
|
HOLD_det_r <= HOLD_det;
|
659 |
|
|
HOLD_det_r2 <= HOLD_det_r;
|
660 |
|
|
HOLD_det_r3 <= HOLD_det_r2;
|
661 |
|
|
HOLD_det_r4 <= HOLD_det_r3;
|
662 |
|
|
TWO_HOLD_det_r <= TWO_HOLD_det;
|
663 |
|
|
end if;
|
664 |
|
|
end if;
|
665 |
|
|
end process RX_FRAME_STATE_PROC;
|
666 |
|
|
|
667 |
|
|
-----------------------------------------------------------------------------
|
668 |
|
|
-- PROCESS: RX_FRAME_LOGIC_PROC
|
669 |
|
|
-- PURPOSE: Receive FRAME from disk and unpack the FIS
|
670 |
|
|
-----------------------------------------------------------------------------
|
671 |
|
|
RX_FRAME_LOGIC_PROC : process (rx_frame_curr, sync_count_rx, ALIGN_det, HOLD_det,
|
672 |
|
|
HOLD_stop_after_ALIGN_det,
|
673 |
|
|
SOF_det, EOF_det, HOLD_start_det, HOLD_stop_det, SYNC_det,
|
674 |
|
|
start_rx, LINKUP, rx_datain, rx_sector_count, sector_count
|
675 |
|
|
) is
|
676 |
|
|
begin
|
677 |
|
|
-- Register _next to current signals
|
678 |
|
|
rx_frame_next <= rx_frame_curr;
|
679 |
|
|
sync_count_rx_next <= sync_count_rx;
|
680 |
|
|
rx_done_next <= rx_done;
|
681 |
|
|
prim_type_rx_next <= prim_type_rx;
|
682 |
|
|
rx_fifo_we_next <= '0';
|
683 |
|
|
---------------------------------------------------------------------------
|
684 |
|
|
-- Finite State Machine
|
685 |
|
|
---------------------------------------------------------------------------
|
686 |
|
|
case (rx_frame_curr) is
|
687 |
|
|
|
688 |
|
|
-- x0
|
689 |
|
|
when idle =>
|
690 |
|
|
rx_done_next <= '0';
|
691 |
|
|
prim_type_rx_next <= SYNC;
|
692 |
|
|
if (start_rx = '1') then
|
693 |
|
|
--if (master_fsm_curr = capture_dev_sign) then
|
694 |
|
|
rx_frame_next <= send_R_RDY;
|
695 |
|
|
--else
|
696 |
|
|
-- rx_frame_next <= wait_for_X_RDY;
|
697 |
|
|
--end if;
|
698 |
|
|
end if;
|
699 |
|
|
|
700 |
|
|
-- x6
|
701 |
|
|
--Wait for X_RDY before sending R_RDY
|
702 |
|
|
when wait_for_X_RDY =>
|
703 |
|
|
prim_type_rx_next <= SYNC;
|
704 |
|
|
if (X_RDY_det = '1') then
|
705 |
|
|
rx_frame_next <= send_R_RDY;
|
706 |
|
|
end if;
|
707 |
|
|
|
708 |
|
|
-- x1
|
709 |
|
|
when send_R_RDY =>
|
710 |
|
|
--Send R_RDY to get device signature
|
711 |
|
|
prim_type_rx_next <= R_RDY;
|
712 |
|
|
|
713 |
|
|
if (SOF_det = '1') then
|
714 |
|
|
rx_frame_next <= send_R_IP;
|
715 |
|
|
end if;
|
716 |
|
|
|
717 |
|
|
-- x2
|
718 |
|
|
when send_R_IP =>
|
719 |
|
|
--Send R_IP to indicate Reception in Progress
|
720 |
|
|
prim_type_rx_next <= R_IP;
|
721 |
|
|
|
722 |
|
|
rx_fifo_we_next <= '1';
|
723 |
|
|
|
724 |
|
|
if (ALIGN_det = '1' or HOLD_det = '1') then
|
725 |
|
|
rx_fifo_we_next <= '0';
|
726 |
|
|
end if;
|
727 |
|
|
|
728 |
|
|
if (EOF_det = '1') then
|
729 |
|
|
rx_fifo_we_next <= '0';
|
730 |
|
|
rx_frame_next <= send_R_OK;
|
731 |
|
|
end if;
|
732 |
|
|
|
733 |
|
|
-- Check for 2 HOLD primitives followed by CONT which indicates FIS pause
|
734 |
|
|
if (HOLD_start_det = '1') then
|
735 |
|
|
rx_fifo_we_next <= '0';
|
736 |
|
|
rx_frame_next <= send_HOLD_ACK;
|
737 |
|
|
end if;
|
738 |
|
|
|
739 |
|
|
-- x3
|
740 |
|
|
when send_HOLD_ACK =>
|
741 |
|
|
-- Send HOLD ACK to Acknowledge FIS pause
|
742 |
|
|
prim_type_rx_next <= HOLD_ACK;
|
743 |
|
|
if (HOLD_stop_after_ALIGN_det = '1') then
|
744 |
|
|
rx_fifo_we_next <= '1';
|
745 |
|
|
rx_frame_next <= send_R_IP;
|
746 |
|
|
end if;
|
747 |
|
|
if (HOLD_stop_det = '1') then
|
748 |
|
|
rx_frame_next <= send_R_IP;
|
749 |
|
|
end if;
|
750 |
|
|
|
751 |
|
|
-- x4
|
752 |
|
|
when send_R_OK =>
|
753 |
|
|
-- Send R_OK to indicate good frame
|
754 |
|
|
prim_type_rx_next <= R_OK;
|
755 |
|
|
|
756 |
|
|
if (SYNC_det = '1') then
|
757 |
|
|
if (master_fsm_curr = D2H_DATA_FIS) then
|
758 |
|
|
if (rx_sector_count < conv_std_logic_vector(sector_count,16)) then
|
759 |
|
|
rx_frame_next <= send_R_RDY;
|
760 |
|
|
else
|
761 |
|
|
rx_done_next <= '1';
|
762 |
|
|
rx_frame_next <= idle;
|
763 |
|
|
end if;
|
764 |
|
|
else
|
765 |
|
|
rx_frame_next <= send_SYNC;
|
766 |
|
|
end if;
|
767 |
|
|
end if;
|
768 |
|
|
|
769 |
|
|
-- x5
|
770 |
|
|
when send_SYNC =>
|
771 |
|
|
-- Send SYNC to indicate host idle
|
772 |
|
|
prim_type_rx_next <= SYNC;
|
773 |
|
|
|
774 |
|
|
if (sync_count_rx = SYNC_COUNT_VALUE) then
|
775 |
|
|
rx_done_next <= '1';
|
776 |
|
|
sync_count_rx_next <= (others => '0');
|
777 |
|
|
rx_frame_next <= idle;
|
778 |
|
|
else
|
779 |
|
|
sync_count_rx_next <= sync_count_rx + 1;
|
780 |
|
|
end if;
|
781 |
|
|
|
782 |
|
|
-- x6
|
783 |
|
|
when dead =>
|
784 |
|
|
rx_frame_next <= dead;
|
785 |
|
|
|
786 |
|
|
-- x7
|
787 |
|
|
when others =>
|
788 |
|
|
rx_frame_next <= dead;
|
789 |
|
|
|
790 |
|
|
end case;
|
791 |
|
|
end process RX_FRAME_LOGIC_PROC;
|
792 |
|
|
|
793 |
|
|
-- Counter for number of received sectors (used when number of RX sectors exceeds max 16 in one data FIS)
|
794 |
|
|
RX_SECTOR_CNT: process(sata_user_clk) is
|
795 |
|
|
begin
|
796 |
|
|
if ((sata_user_clk'event) and (sata_user_clk = '1')) then
|
797 |
|
|
if (sw_reset = '1' or new_cmd = '1') then
|
798 |
|
|
dword_count <= (others => '0');
|
799 |
|
|
rx_sector_count <= (others => '0');
|
800 |
|
|
elsif ((dword_count < (SECTOR_NDWORDS-1)) and (master_fsm_curr = D2H_DATA_FIS) and (rx_fifo_we_next = '1')) then
|
801 |
|
|
dword_count <= dword_count + 1;
|
802 |
|
|
elsif (dword_count = (SECTOR_NDWORDS-1)) then
|
803 |
|
|
dword_count <= (others => '0');
|
804 |
|
|
rx_sector_count <= rx_sector_count + 1;
|
805 |
|
|
elsif (EOF_det = '1') then
|
806 |
|
|
dword_count <= (others => '0');
|
807 |
|
|
else
|
808 |
|
|
dword_count <= dword_count;
|
809 |
|
|
rx_sector_count <= rx_sector_count;
|
810 |
|
|
end if;
|
811 |
|
|
end if;
|
812 |
|
|
end process RX_SECTOR_CNT;
|
813 |
|
|
|
814 |
|
|
|
815 |
|
|
-- DATA FIS DWORD Counter for stripping off DATA FIS header and CRC
|
816 |
|
|
DATA_FIS_DWORD_CNT: process(sata_user_clk) is
|
817 |
|
|
begin
|
818 |
|
|
if ((sata_user_clk'event) and (sata_user_clk = '1')) then
|
819 |
|
|
if (sw_reset = '1') then
|
820 |
|
|
DATA_FIS_dword_count <= (others => '0');
|
821 |
|
|
dword_count_init_value <= (others => '0');
|
822 |
|
|
elsif ((master_fsm_curr = D2H_DATA_FIS) and (DATA_FIS_dword_count < dword_count_value)) then
|
823 |
|
|
if (descrambler_dout_we = '1') then
|
824 |
|
|
DATA_FIS_dword_count <= DATA_FIS_dword_count + 1;
|
825 |
|
|
else
|
826 |
|
|
DATA_FIS_dword_count <= DATA_FIS_dword_count;
|
827 |
|
|
end if;
|
828 |
|
|
elsif ((DATA_FIS_dword_count = dword_count_value) and (master_fsm_curr = D2H_DATA_FIS)) then
|
829 |
|
|
if(dword_count_init_value >= NDWORDS_PER_DATA_FIS_32) then
|
830 |
|
|
dword_count_init_value <= (dword_count_init_value - NDWORDS_PER_DATA_FIS_32);
|
831 |
|
|
end if;
|
832 |
|
|
DATA_FIS_dword_count <= (others => '0');
|
833 |
|
|
else
|
834 |
|
|
DATA_FIS_dword_count <= (others => '0');
|
835 |
|
|
end if;
|
836 |
|
|
|
837 |
|
|
if(new_cmd = '1') then
|
838 |
|
|
dword_count_init_value <= conv_std_logic_vector((SECTOR_NDWORDS * sector_count), 32);
|
839 |
|
|
dword_count_value <= (others => '0');
|
840 |
|
|
elsif(dword_count_init_value < NDWORDS_PER_DATA_FIS_32) then
|
841 |
|
|
dword_count_value <= dword_count_init_value(16 to 31) + conv_std_logic_vector(1,16);
|
842 |
|
|
elsif(dword_count_init_value >= NDWORDS_PER_DATA_FIS_32) then
|
843 |
|
|
dword_count_value <= NDWORDS_PER_DATA_FIS + 1;
|
844 |
|
|
end if;
|
845 |
|
|
end if;
|
846 |
|
|
end process DATA_FIS_DWORD_CNT;
|
847 |
|
|
|
848 |
|
|
-----------------------------------------------------------------------------
|
849 |
|
|
-- PROCESS: TX_FRAME_VALUE_PROC
|
850 |
|
|
-- PURPOSE: ChipScope State Indicator Signal
|
851 |
|
|
-----------------------------------------------------------------------------
|
852 |
|
|
TX_FRAME_VALUE_PROC : process (tx_frame_curr) is
|
853 |
|
|
begin
|
854 |
|
|
case (tx_frame_curr) is
|
855 |
|
|
when idle => tx_frame_value <= x"0";
|
856 |
|
|
when send_X_RDY => tx_frame_value <= x"1";
|
857 |
|
|
when send_SOF => tx_frame_value <= x"2";
|
858 |
|
|
when send_FIS => tx_frame_value <= x"3";
|
859 |
|
|
when send_EOF => tx_frame_value <= x"4";
|
860 |
|
|
when send_WTRM => tx_frame_value <= x"5";
|
861 |
|
|
when send_SYNC => tx_frame_value <= x"6";
|
862 |
|
|
when send_HOLD_ACK => tx_frame_value <= x"7";
|
863 |
|
|
when send_HOLD => tx_frame_value <= x"8";
|
864 |
|
|
when dead => tx_frame_value <= x"9";
|
865 |
|
|
when others => tx_frame_value <= x"A";
|
866 |
|
|
end case;
|
867 |
|
|
end process TX_FRAME_VALUE_PROC;
|
868 |
|
|
|
869 |
|
|
-----------------------------------------------------------------------------
|
870 |
|
|
-- PROCESS: TX_FRAME_STATE_PROC
|
871 |
|
|
-- PURPOSE: Registering Signals and Next State
|
872 |
|
|
-----------------------------------------------------------------------------
|
873 |
|
|
TX_FRAME_STATE_PROC : process (sata_user_clk)
|
874 |
|
|
begin
|
875 |
|
|
if ((sata_user_clk'event) and (sata_user_clk = '1')) then
|
876 |
|
|
if (sw_reset = '1') then
|
877 |
|
|
--Initializing internal signals
|
878 |
|
|
tx_frame_curr <= idle;
|
879 |
|
|
sync_count_tx <= (others => '0');
|
880 |
|
|
rx_tx_state_sel <= '0';
|
881 |
|
|
tx_done <= '0';
|
882 |
|
|
tx_fifo_re <= '0';
|
883 |
|
|
frame_err <= '0';
|
884 |
|
|
tx_err <= '0';
|
885 |
|
|
replay_buffer_clear <= '0';
|
886 |
|
|
prim_type_tx <= (others => '0');
|
887 |
|
|
FIS_word_count <= (others => '0');
|
888 |
|
|
tx_sector_count <= (others => '0');
|
889 |
|
|
elsif(new_cmd = '1') then
|
890 |
|
|
tx_sector_count <= (others => '0');
|
891 |
|
|
else
|
892 |
|
|
-- Register all Current Signals to their _next Signals
|
893 |
|
|
tx_frame_curr <= tx_frame_next;
|
894 |
|
|
sync_count_tx <= sync_count_tx_next;
|
895 |
|
|
rx_tx_state_sel <= rx_tx_state_sel_next;
|
896 |
|
|
tx_done <= tx_done_next;
|
897 |
|
|
tx_fifo_re <= tx_fifo_re_next;
|
898 |
|
|
frame_err <= frame_err_next;
|
899 |
|
|
tx_err <= tx_err_next;
|
900 |
|
|
replay_buffer_clear <= replay_buffer_clear_next;
|
901 |
|
|
prim_type_tx <= prim_type_tx_next;
|
902 |
|
|
FIS_word_count <= FIS_word_count_next;
|
903 |
|
|
tx_sector_count <= tx_sector_count_next;
|
904 |
|
|
end if;
|
905 |
|
|
end if;
|
906 |
|
|
end process TX_FRAME_STATE_PROC;
|
907 |
|
|
|
908 |
|
|
-----------------------------------------------------------------------------
|
909 |
|
|
-- PROCESS: TX_FRAME_LOGIC_PROC
|
910 |
|
|
-- PURPOSE: Next State and Output Logic
|
911 |
|
|
-----------------------------------------------------------------------------
|
912 |
|
|
TX_FRAME_LOGIC_PROC : process (tx_frame_curr, FIS_word_count, sector_count,
|
913 |
|
|
tx_sector_count,
|
914 |
|
|
R_RDY_det, R_OK_det, sync_count_tx, start_tx,
|
915 |
|
|
LINKUP, frame_err
|
916 |
|
|
) is
|
917 |
|
|
begin
|
918 |
|
|
-- Register _next to current signals
|
919 |
|
|
tx_frame_next <= tx_frame_curr;
|
920 |
|
|
sync_count_tx_next <= sync_count_tx;
|
921 |
|
|
rx_tx_state_sel_next <= rx_tx_state_sel;
|
922 |
|
|
tx_fifo_re_next <= tx_fifo_re;
|
923 |
|
|
tx_done_next <= tx_done;
|
924 |
|
|
frame_err_next <= frame_err;
|
925 |
|
|
tx_err_next <= tx_err;
|
926 |
|
|
replay_buffer_clear_next <= replay_buffer_clear;
|
927 |
|
|
prim_type_tx_next <= prim_type_tx;
|
928 |
|
|
FIS_word_count_next <= FIS_word_count;
|
929 |
|
|
tx_sector_count_next <= tx_sector_count;
|
930 |
10 |
ashwin_men |
tx_charisk_TX_FRAME <= '1';
|
931 |
2 |
ashwin_men |
---------------------------------------------------------------------------
|
932 |
|
|
-- Finite State Machine
|
933 |
|
|
---------------------------------------------------------------------------
|
934 |
|
|
case (tx_frame_curr) is
|
935 |
|
|
|
936 |
|
|
-- x0
|
937 |
|
|
when idle =>
|
938 |
|
|
tx_done_next <= '0';
|
939 |
|
|
tx_err_next <= '0';
|
940 |
|
|
replay_buffer_clear_next <= '0';
|
941 |
|
|
prim_type_tx_next <= SYNC;
|
942 |
|
|
FIS_word_count_next <= (others => '0');
|
943 |
|
|
|
944 |
|
|
if (start_tx = '1') then
|
945 |
|
|
rx_tx_state_sel_next <= '1';
|
946 |
|
|
tx_frame_next <= send_X_RDY;
|
947 |
|
|
end if;
|
948 |
|
|
|
949 |
|
|
-- x1
|
950 |
|
|
when send_X_RDY =>
|
951 |
|
|
-- Send X_RDY to indicate host ready to transmit
|
952 |
|
|
prim_type_tx_next <= X_RDY;
|
953 |
|
|
if (R_RDY_det = '1') then
|
954 |
|
|
tx_frame_next <= send_SOF;
|
955 |
|
|
end if;
|
956 |
|
|
|
957 |
|
|
-- x2
|
958 |
|
|
when send_SOF =>
|
959 |
|
|
--Send SOF to indicate start of new FRAME
|
960 |
|
|
prim_type_tx_next <= SOF;
|
961 |
|
|
if (align_en_out = '0') then
|
962 |
|
|
tx_frame_next <= send_FIS;
|
963 |
|
|
end if;
|
964 |
|
|
|
965 |
|
|
-- x3
|
966 |
|
|
when send_FIS =>
|
967 |
10 |
ashwin_men |
tx_charisk_TX_FRAME <= '0';
|
968 |
2 |
ashwin_men |
--Send FIS data
|
969 |
|
|
prim_type_tx_next <= FIS;
|
970 |
|
|
-- ALIGN primitives after 256 DWORDS
|
971 |
|
|
if (align_en_out = '1' or tx_fifo_almost_empty = '1') then
|
972 |
|
|
FIS_word_count_next <= FIS_word_count;
|
973 |
|
|
tx_fifo_re_next <= '0';
|
974 |
|
|
else
|
975 |
|
|
FIS_word_count_next <= FIS_word_count + '1';
|
976 |
|
|
tx_fifo_re_next <= '1';
|
977 |
|
|
end if;
|
978 |
|
|
-- Receive buffer empty condition
|
979 |
|
|
if (HOLD_start_det = '1') then
|
980 |
|
|
tx_frame_next <= send_HOLD_ACK;
|
981 |
|
|
end if;
|
982 |
|
|
-- Transmit buffer empty condition
|
983 |
|
|
if (tx_fifo_almost_empty = '1') then
|
984 |
|
|
if (align_en_out = '0') then
|
985 |
10 |
ashwin_men |
tx_charisk_TX_FRAME <= '1';
|
986 |
2 |
ashwin_men |
prim_type_tx_next <= HOLD;
|
987 |
|
|
tx_frame_next <= send_HOLD;
|
988 |
|
|
end if;
|
989 |
|
|
end if;
|
990 |
|
|
-- Transmitted sector count
|
991 |
|
|
if(((conv_integer(FIS_word_count) mod SECTOR_NDWORDS)=0) and (conv_integer(FIS_word_count)>0) and (align_en_out='0') and (tx_fifo_almost_empty='0')) then
|
992 |
|
|
tx_sector_count_next <= tx_sector_count + 1;
|
993 |
|
|
else
|
994 |
|
|
tx_sector_count_next <= tx_sector_count;
|
995 |
|
|
end if;
|
996 |
|
|
if ((tx_sector_count >= conv_std_logic_vector(sector_count, 16)) or (FIS_word_count >= FIS_count_value)) then
|
997 |
|
|
if (align_en_out = '0') then
|
998 |
10 |
ashwin_men |
tx_charisk_TX_FRAME <= '0';
|
999 |
2 |
ashwin_men |
FIS_word_count_next <= (others => '0');
|
1000 |
|
|
tx_fifo_re_next <= '1';
|
1001 |
|
|
prim_type_tx_next <= FIS;
|
1002 |
|
|
tx_frame_next <= send_EOF;
|
1003 |
|
|
end if;
|
1004 |
|
|
end if;
|
1005 |
|
|
|
1006 |
|
|
-- x7
|
1007 |
|
|
when send_HOLD_ACK =>
|
1008 |
|
|
-- Send HOLD ACK to Acknowledge FIS pause
|
1009 |
|
|
prim_type_tx_next <= HOLD_ACK;
|
1010 |
|
|
tx_fifo_re_next <= '0';
|
1011 |
|
|
--if (HOLD_stop_det = '1') then
|
1012 |
|
|
if (R_IP_det = '1') then
|
1013 |
|
|
tx_frame_next <= send_FIS;
|
1014 |
|
|
end if;
|
1015 |
|
|
|
1016 |
|
|
-- x8
|
1017 |
|
|
when send_HOLD =>
|
1018 |
|
|
-- Send HOLD to indicate transmit buffer empty
|
1019 |
|
|
prim_type_tx_next <= HOLD;
|
1020 |
|
|
tx_fifo_re_next <= '0';
|
1021 |
|
|
if (tx_fifo_empty = '0') then
|
1022 |
|
|
tx_frame_next <= send_FIS;
|
1023 |
|
|
end if;
|
1024 |
|
|
|
1025 |
|
|
-- x4
|
1026 |
|
|
when send_EOF =>
|
1027 |
|
|
--Send EOF to indicate end of FRAME
|
1028 |
|
|
tx_fifo_re_next <= '0';
|
1029 |
|
|
prim_type_tx_next <= EOF;
|
1030 |
|
|
if (align_en_out = '0') then
|
1031 |
|
|
tx_frame_next <= send_WTRM;
|
1032 |
|
|
end if;
|
1033 |
|
|
|
1034 |
|
|
-- x5
|
1035 |
|
|
when send_WTRM =>
|
1036 |
|
|
-- Send WTRM to indicate Waiting for Frame Termination
|
1037 |
|
|
prim_type_tx_next <= WTRM;
|
1038 |
|
|
|
1039 |
|
|
if (R_OK_det = '1' or R_ERR_det = '1' or SYNC_det = '1') then
|
1040 |
|
|
if (R_ERR_det = '1' or SYNC_det = '1') then
|
1041 |
|
|
if (master_fsm_curr = H2D_REG_FIS) then
|
1042 |
|
|
frame_err_next <= '1';
|
1043 |
|
|
else
|
1044 |
|
|
frame_err_next <= '0';
|
1045 |
|
|
end if;
|
1046 |
|
|
end if;
|
1047 |
|
|
if (R_OK_det = '1') then
|
1048 |
|
|
replay_buffer_clear_next <= '1';
|
1049 |
|
|
frame_err_next <= '0';
|
1050 |
|
|
end if;
|
1051 |
|
|
tx_frame_next <= send_SYNC;
|
1052 |
|
|
end if;
|
1053 |
|
|
|
1054 |
|
|
-- x6
|
1055 |
|
|
when send_SYNC =>
|
1056 |
|
|
-- Send SYNC to indicate host idle
|
1057 |
|
|
prim_type_tx_next <= SYNC;
|
1058 |
|
|
|
1059 |
|
|
if (sync_count_tx = SYNC_COUNT_VALUE) then
|
1060 |
|
|
sync_count_tx_next <= (others => '0');
|
1061 |
|
|
if (frame_err = '1') then
|
1062 |
|
|
tx_err_next <= '1';
|
1063 |
|
|
else
|
1064 |
|
|
tx_done_next <= '1';
|
1065 |
|
|
end if;
|
1066 |
|
|
rx_tx_state_sel_next <= '0';
|
1067 |
|
|
tx_frame_next <= idle;
|
1068 |
|
|
else
|
1069 |
|
|
sync_count_tx_next <= sync_count_tx + 1;
|
1070 |
|
|
end if;
|
1071 |
|
|
|
1072 |
|
|
-- x8
|
1073 |
|
|
when dead =>
|
1074 |
|
|
tx_frame_next <= dead;
|
1075 |
|
|
|
1076 |
|
|
-- x9
|
1077 |
|
|
when others =>
|
1078 |
|
|
tx_frame_next <= dead;
|
1079 |
|
|
|
1080 |
|
|
end case;
|
1081 |
|
|
end process TX_FRAME_LOGIC_PROC;
|
1082 |
|
|
|
1083 |
|
|
-- ASYNCHRONOUS MUXES
|
1084 |
|
|
tx_charisk_RX_FRAME <= '1';
|
1085 |
10 |
ashwin_men |
--tx_charisk_TX_FRAME <= '0' when (((tx_frame_curr = send_FIS) and (tx_fifo_almost_empty = '0')) or ((tx_frame_curr=send_FIS) and
|
1086 |
|
|
-- (tx_fifo_almost_empty = '1') and (master_fsm_curr = H2D_REG_FIS))) else '1';
|
1087 |
2 |
ashwin_men |
--tx_charisk_out <= '0' when ((tx_frame_curr = send_FIS) or (prim_type_tx = PRIM_SCRM)) else tx_charisk_RX_FRAME when (rx_tx_state_sel = '0') else tx_charisk_TX_FRAME;
|
1088 |
|
|
tx_charisk_out <= tx_charisk_RX_FRAME when (rx_tx_state_sel = '0') else tx_charisk_TX_FRAME;
|
1089 |
|
|
prim_type <= prim_type_rx when (rx_tx_state_sel = '0') else prim_type_tx;
|
1090 |
|
|
-- ASYNCHRONOUS MUXES
|
1091 |
|
|
|
1092 |
|
|
-- Primitive detection
|
1093 |
|
|
ALIGN_det <= '1' when (rx_datain = x"7B4A4ABC") else '0';
|
1094 |
|
|
SYNC_det <= '1' when (rx_datain = x"B5B5957C") else '0';
|
1095 |
|
|
R_RDY_det <= '1' when (rx_datain = x"4A4A957C") else '0';
|
1096 |
|
|
R_IP_det <= '1' when (rx_datain = x"5555B57C") else '0';
|
1097 |
|
|
R_OK_det <= '1' when (rx_datain = x"3535B57C") else '0';
|
1098 |
|
|
R_ERR_det <= '1' when (rx_datain = x"5656B57C") else '0';
|
1099 |
|
|
SOF_det <= '1' when (rx_datain = x"3737B57C") else '0';
|
1100 |
|
|
EOF_det <= '1' when (rx_datain = x"D5D5B57C") else '0';
|
1101 |
|
|
X_RDY_det <= '1' when (rx_datain = x"5757B57C") else '0';
|
1102 |
|
|
WTRM_det <= '1' when (rx_datain = x"5858B57C") else '0';
|
1103 |
|
|
CONT_det <= '1' when (rx_datain = x"9999AA7C") else '0';
|
1104 |
|
|
HOLD_det <= '1' when (rx_datain = x"D5D5AA7C") else '0';
|
1105 |
|
|
HOLD_start_det <= '1' when (((TWO_HOLD_det_r = '1') and (CONT_det = '1')) or (CORNER_CASE_HOLD = '1')) else '0';
|
1106 |
|
|
TWO_HOLD_det <= '1' when ((rx_datain = x"D5D5AA7C") and (HOLD_det_r = '1')) else '0';
|
1107 |
|
|
HOLD_stop_det <= '1' when ((rx_datain = x"D5D5AA7C") and (ALIGN_det_r = '0') and (TWO_HOLD_det = '0')) else '0';
|
1108 |
|
|
HOLD_stop_after_ALIGN_det <= '1' when ((HOLD_det_r = '1') and (ALIGN_det_r2 = '1') and (ALIGN_det_r = '0') and (TWO_HOLD_det = '0')) or ((TWO_HOLD_det_r = '1') and (CONT_det = '0')) else '0';
|
1109 |
|
|
-- Corner Case
|
1110 |
|
|
-- ALIGN primitives are received between two HOLD primitives or between 2 HOLD and a CONT primitive
|
1111 |
|
|
CORNER_CASE_HOLD <= '1' when ((CONT_det = '1') and (HOLD_det_r4 = '1')) else '0';
|
1112 |
|
|
|
1113 |
|
|
|
1114 |
|
|
-- SATA Primitives
|
1115 |
|
|
-- SYNC
|
1116 |
|
|
tx_sync <= x"B5B5957C";
|
1117 |
|
|
|
1118 |
|
|
-- R_RDY
|
1119 |
|
|
tx_r_rdy <= x"4A4A957C";
|
1120 |
|
|
|
1121 |
|
|
-- R_OK
|
1122 |
|
|
tx_r_ok <= x"3535B57C";
|
1123 |
|
|
|
1124 |
|
|
-- R_ERR
|
1125 |
|
|
tx_r_err <= x"5656B57C";
|
1126 |
|
|
|
1127 |
|
|
-- R_IP
|
1128 |
|
|
tx_r_ip <= x"5555B57C";
|
1129 |
|
|
|
1130 |
|
|
-- X_RDY
|
1131 |
|
|
tx_x_rdy <= x"5757B57C";
|
1132 |
|
|
|
1133 |
|
|
-- CONT
|
1134 |
|
|
tx_cont <= x"9999AA7C";
|
1135 |
|
|
|
1136 |
|
|
-- WTRM
|
1137 |
|
|
tx_wtrm <= x"5858B57C";
|
1138 |
|
|
|
1139 |
|
|
-- SOF
|
1140 |
|
|
tx_sof <= x"3737B57C";
|
1141 |
|
|
|
1142 |
|
|
-- EOF
|
1143 |
|
|
tx_eof <= x"D5D5B57C";
|
1144 |
|
|
|
1145 |
|
|
-- HOLD
|
1146 |
|
|
tx_hold <= x"D5D5AA7C";
|
1147 |
|
|
|
1148 |
|
|
-- HOLD_ACK
|
1149 |
|
|
tx_hold_ack <= x"9595AA7C";
|
1150 |
|
|
|
1151 |
|
|
-- Output Mux
|
1152 |
|
|
OUTPUT_MUX_i: entity work.mux_161
|
1153 |
|
|
generic map
|
1154 |
|
|
(
|
1155 |
|
|
DATA_WIDTH => 32
|
1156 |
|
|
)
|
1157 |
|
|
port map
|
1158 |
|
|
(
|
1159 |
|
|
a => tx_sync,
|
1160 |
|
|
b => tx_r_rdy,
|
1161 |
|
|
c => tx_r_ip,
|
1162 |
|
|
d => tx_r_ok,
|
1163 |
|
|
e => tx_r_err,
|
1164 |
|
|
f => tx_x_rdy,
|
1165 |
|
|
g => tx_wtrm,
|
1166 |
|
|
h => tx_hold,
|
1167 |
|
|
i => tx_hold_ack,
|
1168 |
|
|
j => tx_cont,
|
1169 |
|
|
k => tx_sof,
|
1170 |
|
|
l => tx_eof,
|
1171 |
|
|
m => tx_fifo_dout,
|
1172 |
|
|
--n => tx_prim_scrm,
|
1173 |
|
|
n => (others => '0'),
|
1174 |
|
|
o => (others => '0'),
|
1175 |
|
|
p => (others => '0'),
|
1176 |
|
|
sel=> output_mux_sel,
|
1177 |
|
|
output=> tx_dataout
|
1178 |
|
|
);
|
1179 |
|
|
|
1180 |
|
|
output_mux_sel <= prim_type;
|
1181 |
|
|
|
1182 |
|
|
-------------------------------------------------------------------------------
|
1183 |
|
|
-- LINK LAYER
|
1184 |
|
|
-------------------------------------------------------------------------------
|
1185 |
|
|
---------------------------------------------------------------------------
|
1186 |
|
|
-- Pre-DeScramble RX FIFO from PHY Layer
|
1187 |
|
|
---------------------------------------------------------------------------
|
1188 |
|
|
rx_fifo_din <= rx_datain;
|
1189 |
|
|
rx_fifo_re <= descrambler_din_re_r;
|
1190 |
|
|
|
1191 |
|
|
RX_FIFO : rx_tx_fifo
|
1192 |
|
|
port map (
|
1193 |
|
|
clk => sata_user_clk,
|
1194 |
|
|
rst => sw_reset,
|
1195 |
|
|
rd_en => rx_fifo_re,
|
1196 |
|
|
din => rx_fifo_din,
|
1197 |
|
|
wr_en => rx_fifo_we_next,
|
1198 |
|
|
dout => rx_fifo_dout,
|
1199 |
|
|
almost_empty => rx_fifo_almost_empty,
|
1200 |
|
|
empty => rx_fifo_empty,
|
1201 |
|
|
full => rx_fifo_full,
|
1202 |
|
|
prog_full => rx_fifo_prog_full,
|
1203 |
|
|
data_count => rx_fifo_data_count
|
1204 |
|
|
);
|
1205 |
|
|
|
1206 |
|
|
---------------------------------------------------------------------------
|
1207 |
|
|
-- DESCRAMBLER
|
1208 |
|
|
---------------------------------------------------------------------------
|
1209 |
|
|
--descrambler_din(0 to 15) <= rx_fifo_dout(16 to 31);
|
1210 |
|
|
--descrambler_din(16 to 31) <= rx_fifo_dout(0 to 15);
|
1211 |
|
|
descrambler_din <= rx_fifo_dout;
|
1212 |
|
|
descrambler_en <= not(rx_fifo_almost_empty);
|
1213 |
|
|
descrambler_reset <= '1' when ((start_rx='1') or ((rx_frame_curr = send_R_OK) and (SYNC_det = '1'))) else '0';
|
1214 |
|
|
|
1215 |
|
|
DESCRAMBLER_i: entity work.scrambler
|
1216 |
|
|
generic map(
|
1217 |
|
|
CHIPSCOPE => FALSE
|
1218 |
|
|
)
|
1219 |
|
|
port map(
|
1220 |
|
|
-- Clock and Reset Signals
|
1221 |
|
|
clk => sata_user_clk,
|
1222 |
|
|
reset => descrambler_reset,
|
1223 |
|
|
-- ChipScope ILA / Trigger Signals
|
1224 |
|
|
scrambler_ila_control => descrambler_ila_control,
|
1225 |
|
|
---------------------------------------
|
1226 |
|
|
-- Signals from/to Sata Link Layer FIFOs
|
1227 |
|
|
prim_scrambler => '0',
|
1228 |
|
|
scrambler_en => descrambler_en,
|
1229 |
|
|
din_re => descrambler_din_re,
|
1230 |
|
|
data_in => descrambler_din,
|
1231 |
|
|
data_out => descrambler_dout,
|
1232 |
|
|
dout_we => descrambler_dout_we
|
1233 |
|
|
);
|
1234 |
|
|
|
1235 |
|
|
---------------------------------------------------------------------------
|
1236 |
|
|
-- Post-DeScramble Read FIFO to Command Layer
|
1237 |
|
|
---------------------------------------------------------------------------
|
1238 |
|
|
read_fifo_din <= descrambler_dout;
|
1239 |
|
|
read_fifo_we <= descrambler_dout_we when ((master_fsm_curr = D2H_DATA_FIS) and (DATA_FIS_dword_count > 0) and (DATA_FIS_dword_count < dword_count_value)) else '0';
|
1240 |
|
|
|
1241 |
|
|
READ_FIFO_i : read_write_fifo
|
1242 |
|
|
port map (
|
1243 |
|
|
clk => sata_user_clk,
|
1244 |
|
|
rst => sw_reset,
|
1245 |
|
|
rd_en => read_fifo_re,
|
1246 |
|
|
din => read_fifo_din,
|
1247 |
|
|
wr_en => read_fifo_we,
|
1248 |
|
|
dout => read_fifo_dout,
|
1249 |
|
|
almost_empty => read_fifo_almost_empty,
|
1250 |
|
|
empty => read_fifo_empty_i,
|
1251 |
|
|
full => read_fifo_full,
|
1252 |
|
|
prog_full => read_fifo_prog_full
|
1253 |
|
|
);
|
1254 |
|
|
-- Data Output to Command Layer
|
1255 |
|
|
sata_dout <= read_fifo_dout;
|
1256 |
|
|
-- Input from Command Layer
|
1257 |
|
|
read_fifo_re <= sata_dout_re;
|
1258 |
|
|
|
1259 |
|
|
read_fifo_empty <= read_fifo_empty_i;
|
1260 |
|
|
---------------------------------------------------------------------------
|
1261 |
|
|
-- Pre-Scramble Write FIFO from Command Layer
|
1262 |
|
|
---------------------------------------------------------------------------
|
1263 |
|
|
write_fifo_we <= sata_din_we;
|
1264 |
|
|
write_fifo_din <= sata_din;
|
1265 |
|
|
write_fifo_full <= write_fifo_prog_full;
|
1266 |
|
|
--write_fifo_re <= scrambler_din_re_r when (scrambler_en = '1') else '0';
|
1267 |
|
|
write_fifo_re <= scrambler_din_re_r when ((scrambler_en='1') and (scrambler_count_en_reg_fis='1')) or ((scrambler_count < scrambler_count_value) and (scrambler_count_en_data_fis = '1') and (write_fifo_empty = '0')) else '0';
|
1268 |
|
|
|
1269 |
|
|
WRITE_FIFO_i : read_write_fifo
|
1270 |
|
|
port map (
|
1271 |
|
|
clk => sata_user_clk,
|
1272 |
|
|
rst => sw_reset,
|
1273 |
|
|
din => write_fifo_din,
|
1274 |
|
|
wr_en => write_fifo_we,
|
1275 |
|
|
dout => write_fifo_dout,
|
1276 |
|
|
rd_en => write_fifo_re,
|
1277 |
|
|
almost_empty => write_fifo_almost_empty,
|
1278 |
|
|
empty => write_fifo_empty,
|
1279 |
|
|
full => write_fifo_full_i,
|
1280 |
|
|
prog_full => write_fifo_prog_full
|
1281 |
|
|
);
|
1282 |
|
|
|
1283 |
|
|
---------------------------------------------------------------------------
|
1284 |
|
|
-- CRC
|
1285 |
|
|
---------------------------------------------------------------------------
|
1286 |
|
|
crc_reset <= scrambler_reset;
|
1287 |
|
|
crc_en <= scrambler_dout_we;
|
1288 |
|
|
crc_din <= write_fifo_dout;
|
1289 |
|
|
|
1290 |
|
|
CRC_i : entity work.crc
|
1291 |
|
|
generic map (
|
1292 |
|
|
CHIPSCOPE => FALSE
|
1293 |
|
|
)
|
1294 |
|
|
port map (
|
1295 |
|
|
clk => sata_user_clk,
|
1296 |
|
|
reset => crc_reset,
|
1297 |
|
|
--crc_ila_control => crc_ila_control,
|
1298 |
|
|
crc_en => crc_en,
|
1299 |
|
|
data_in => crc_din,
|
1300 |
|
|
data_out => crc_dout
|
1301 |
|
|
);
|
1302 |
|
|
|
1303 |
|
|
---------------------------------------------------------------------------
|
1304 |
|
|
-- SCRAMBLER
|
1305 |
|
|
---------------------------------------------------------------------------
|
1306 |
|
|
REGISTER_PROCESS : process(sata_user_clk) is
|
1307 |
|
|
begin
|
1308 |
|
|
if sata_user_clk'event and sata_user_clk = '1' then
|
1309 |
|
|
if sw_reset = '1' then
|
1310 |
|
|
scrambler_din_re_r <= '0';
|
1311 |
|
|
descrambler_din_re_r <= '0';
|
1312 |
|
|
crc_dout_r <= (others => '0');
|
1313 |
|
|
else
|
1314 |
|
|
scrambler_din_re_r <= scrambler_din_re;
|
1315 |
|
|
descrambler_din_re_r <= descrambler_din_re;
|
1316 |
|
|
crc_dout_r <= crc_dout;
|
1317 |
|
|
end if;
|
1318 |
|
|
end if;
|
1319 |
|
|
end process REGISTER_PROCESS;
|
1320 |
|
|
|
1321 |
|
|
|
1322 |
|
|
scrambler_count_en_reg_fis <= '1' when (master_fsm_curr = H2D_REG_FIS) else '0';
|
1323 |
|
|
scrambler_count_en_data_fis <= '1' when ((master_fsm_curr = H2D_DATA_FIS) or ((master_fsm_curr = D2H_DMA_ACT_FIS) and (tx_sector_count > 0))) else '0';
|
1324 |
|
|
|
1325 |
|
|
-- To disable scrambler after the REG FIS
|
1326 |
|
|
SCRAMBLER_CNT: process(sata_user_clk) is
|
1327 |
|
|
begin
|
1328 |
|
|
if ((sata_user_clk'event) and (sata_user_clk = '1')) then
|
1329 |
|
|
if (sw_reset = '1') then
|
1330 |
|
|
scrambler_count <= (others => '0');
|
1331 |
|
|
scrambler_count_init_value <= (others => '0');
|
1332 |
|
|
scrambler_count_value <= (others => '0');
|
1333 |
|
|
scrambler_reset_after_FIS <= '0';
|
1334 |
|
|
elsif ((scrambler_count < (REG_FIS_NDWORDS)) and (scrambler_count_en_reg_fis = '1')) then
|
1335 |
|
|
scrambler_count <= scrambler_count + 1;
|
1336 |
|
|
elsif ((scrambler_count < scrambler_count_value) and (scrambler_count_en_data_fis = '1') and (tx_fifo_we = '1') and (write_fifo_empty = '0')) then
|
1337 |
|
|
scrambler_count <= scrambler_count + 1;
|
1338 |
|
|
if (scrambler_count = NDWORDS_PER_DATA_FIS) then
|
1339 |
|
|
scrambler_reset_after_FIS <= '1';
|
1340 |
|
|
end if;
|
1341 |
|
|
elsif (( scrambler_count = (NDWORDS_PER_DATA_FIS+1)) and (scrambler_count_en_data_fis = '1')) then
|
1342 |
|
|
scrambler_count_init_value <= (scrambler_count_init_value - NDWORDS_PER_DATA_FIS_32);
|
1343 |
|
|
scrambler_count <= (others => '0');
|
1344 |
|
|
scrambler_reset_after_FIS <= '0';
|
1345 |
|
|
else
|
1346 |
|
|
scrambler_count <= scrambler_count;
|
1347 |
|
|
end if;
|
1348 |
|
|
|
1349 |
|
|
if (scrambler_reset = '1') then
|
1350 |
|
|
scrambler_count <= (others => '0');
|
1351 |
|
|
scrambler_reset_after_FIS <= '0';
|
1352 |
|
|
end if;
|
1353 |
|
|
|
1354 |
|
|
if(new_cmd = '1') then
|
1355 |
|
|
scrambler_count_init_value <= conv_std_logic_vector((SECTOR_NDWORDS * sector_count), 32);
|
1356 |
|
|
scrambler_count_value <= (others => '0');
|
1357 |
|
|
elsif(scrambler_count_init_value < NDWORDS_PER_DATA_FIS_32) then
|
1358 |
|
|
scrambler_count_value <= scrambler_count_init_value(16 to 31) + conv_std_logic_vector(1,16);
|
1359 |
|
|
elsif(scrambler_count_init_value >= NDWORDS_PER_DATA_FIS_32) then
|
1360 |
|
|
scrambler_count_value <= NDWORDS_PER_DATA_FIS + 1;
|
1361 |
|
|
end if;
|
1362 |
|
|
end if;
|
1363 |
|
|
end process SCRAMBLER_CNT;
|
1364 |
|
|
|
1365 |
|
|
|
1366 |
|
|
scrambler_reset <= (sw_reset or new_cmd or scrambler_reset_after_FIS or (tx_done and scrambler_count_en_reg_fis)) ;
|
1367 |
|
|
scrambler_din <= crc_dout_r when ((scrambler_count = REG_FIS_NDWORDS) and (scrambler_count_en_reg_fis = '1')) or ((scrambler_count = scrambler_count_value) and (scrambler_count_en_data_fis = '1')) else write_fifo_dout;
|
1368 |
|
|
scrambler_en <= not(write_fifo_empty) when (((scrambler_count_en_reg_fis = '1') and (scrambler_count < REG_FIS_NDWORDS))
|
1369 |
|
|
--or ((scrambler_count_en_data_fis = '1') and (scrambler_count = NDWORDS_PER_DATA_FIS) and (tx_fifo_prog_full = '1'))
|
1370 |
|
|
or ((scrambler_count_en_data_fis = '1') and (scrambler_count = (scrambler_count_value - '1'))))
|
1371 |
|
|
else not(write_fifo_almost_empty) when ((scrambler_count_en_data_fis = '1') and (scrambler_count < scrambler_count_value) and (tx_fifo_prog_full = '0'))
|
1372 |
|
|
else '0';
|
1373 |
|
|
-- Corner Case: tx_fifo_almost_full goes high when (scrambler_count = NDWORDS_PER_DATA_FIS)
|
1374 |
|
|
|
1375 |
|
|
SCRAMBLER_i: entity work.scrambler
|
1376 |
|
|
generic map(
|
1377 |
|
|
CHIPSCOPE => FALSE
|
1378 |
|
|
)
|
1379 |
|
|
port map(
|
1380 |
|
|
-- Clock and Reset Signals
|
1381 |
|
|
clk => sata_user_clk,
|
1382 |
|
|
reset => scrambler_reset,
|
1383 |
|
|
-- ChipScope ILA / Trigger Signals
|
1384 |
|
|
scrambler_ila_control => scrambler_ila_control,
|
1385 |
|
|
---------------------------------------
|
1386 |
|
|
-- Signals from/to Sata Link Layer FIFOs
|
1387 |
|
|
prim_scrambler => '0',
|
1388 |
|
|
scrambler_en => scrambler_en,
|
1389 |
|
|
din_re => scrambler_din_re,
|
1390 |
|
|
data_in => scrambler_din,
|
1391 |
|
|
data_out => scrambler_dout,
|
1392 |
|
|
dout_we => scrambler_dout_we
|
1393 |
|
|
);
|
1394 |
|
|
|
1395 |
|
|
---------------------------------------------------------------------------
|
1396 |
|
|
-- Post-Scramble TX FIFO to PHY Layer
|
1397 |
|
|
---------------------------------------------------------------------------
|
1398 |
|
|
-- Input Signals from User Logic
|
1399 |
|
|
tx_fifo_din <= scrambler_dout;
|
1400 |
|
|
tx_fifo_we <= scrambler_dout_we;
|
1401 |
|
|
|
1402 |
|
|
TX_FIFO: rx_tx_fifo
|
1403 |
|
|
port map (
|
1404 |
|
|
clk => sata_user_clk,
|
1405 |
|
|
rst => sw_reset,
|
1406 |
|
|
rd_en => tx_fifo_re,
|
1407 |
|
|
din => tx_fifo_din,
|
1408 |
|
|
wr_en => tx_fifo_we,
|
1409 |
|
|
dout => tx_fifo_dout,
|
1410 |
|
|
almost_empty => tx_fifo_almost_empty,
|
1411 |
|
|
empty => tx_fifo_empty,
|
1412 |
|
|
full => tx_fifo_full,
|
1413 |
|
|
prog_full => tx_fifo_prog_full,
|
1414 |
|
|
data_count => tx_fifo_data_count
|
1415 |
|
|
);
|
1416 |
|
|
|
1417 |
|
|
---------------------------------------------------------------------------
|
1418 |
|
|
-- Sata Phy Instantiation
|
1419 |
|
|
---------------------------------------------------------------------------
|
1420 |
|
|
SATA_PHY_i : sata_phy
|
1421 |
|
|
port map (
|
1422 |
|
|
oob_control_ila_control=> oob_control_ila_control,
|
1423 |
|
|
sata_phy_ila_control => sata_phy_ila_control,
|
1424 |
|
|
REFCLK_PAD_P_IN => REFCLK_PAD_P_IN ,
|
1425 |
|
|
REFCLK_PAD_N_IN => REFCLK_PAD_N_IN ,
|
1426 |
|
|
GTXRESET_IN => GTX_RESET_IN ,
|
1427 |
|
|
PLLLKDET_OUT_N => PLLLKDET_OUT_N ,
|
1428 |
|
|
TXP0_OUT => TXP0_OUT,
|
1429 |
|
|
TXN0_OUT => TXN0_OUT,
|
1430 |
|
|
RXP0_IN => RXP0_IN ,
|
1431 |
|
|
RXN0_IN => RXN0_IN ,
|
1432 |
|
|
DCMLOCKED_OUT => DCMLOCKED_OUT,
|
1433 |
|
|
LINKUP => LINKUP ,
|
1434 |
|
|
LINKUP_led => LINKUP_led ,
|
1435 |
|
|
sata_user_clk => sata_user_clk ,
|
1436 |
|
|
GEN2_led => GEN2_led_i ,
|
1437 |
|
|
align_en_out => align_en_out,
|
1438 |
|
|
tx_datain => tx_dataout,
|
1439 |
|
|
tx_charisk_in => tx_charisk_out,
|
1440 |
|
|
rx_dataout => rx_datain,
|
1441 |
|
|
rx_charisk_out => rx_charisk_in,
|
1442 |
|
|
CurrentState_out => OOB_state,
|
1443 |
|
|
rxelecidle_out => rxelecidle,
|
1444 |
|
|
CLKIN_150 => CLKIN_150
|
1445 |
|
|
);
|
1446 |
|
|
|
1447 |
|
|
sata_user_clk_out <= sata_user_clk;
|
1448 |
|
|
|
1449 |
|
|
-----------------------------------------------------------------------------
|
1450 |
|
|
-- ILA Instantiations
|
1451 |
|
|
-----------------------------------------------------------------------------
|
1452 |
|
|
chipscope_gen_ila : if (CHIPSCOPE) generate
|
1453 |
|
|
SATA_RX_FRAME_ILA_i : sata_rx_frame_ila
|
1454 |
|
|
port map (
|
1455 |
|
|
control => sata_rx_frame_ila_control,
|
1456 |
|
|
clk => sata_user_clk,
|
1457 |
|
|
trig0 => rx_frame_value,
|
1458 |
|
|
trig1 => tx_dataout,
|
1459 |
|
|
trig2 => sync_count_rx,
|
1460 |
|
|
trig3 => master_fsm_value,
|
1461 |
|
|
trig4 => rx_charisk_in,
|
1462 |
|
|
trig5 => OOB_state,
|
1463 |
|
|
trig6 => rx_datain,
|
1464 |
|
|
trig7 => rx_fifo_dout,
|
1465 |
|
|
trig8 => read_fifo_din,
|
1466 |
|
|
trig9 => read_fifo_dout,
|
1467 |
|
|
trig10(0) => SOF_det,
|
1468 |
|
|
trig10(1) => EOF_det,
|
1469 |
|
|
trig10(2) => X_RDY_det,
|
1470 |
|
|
trig10(3) => WTRM_det,
|
1471 |
|
|
trig10(4) => HOLD_start_det,
|
1472 |
|
|
trig10(5) => HOLD_stop_det,
|
1473 |
|
|
trig10(6) => SYNC_det,
|
1474 |
|
|
trig10(7) => CONT_det,
|
1475 |
|
|
trig10(8) => ALIGN_det,
|
1476 |
|
|
trig10(9) => new_cmd,
|
1477 |
|
|
trig10(10) => start_rx,
|
1478 |
|
|
trig10(11) => rx_done,
|
1479 |
|
|
trig10(12) => descrambler_dout_we,
|
1480 |
|
|
trig10(13) => tx_charisk_out,
|
1481 |
|
|
trig10(14) => sw_reset,
|
1482 |
|
|
trig10(15) => LINKUP,
|
1483 |
|
|
trig10(16) => rx_fifo_we_next,
|
1484 |
|
|
trig10(17) => rx_fifo_re,
|
1485 |
|
|
trig10(18) => rx_fifo_empty,
|
1486 |
|
|
trig10(19) => descrambler_reset,
|
1487 |
|
|
trig10(20) => descrambler_en,
|
1488 |
|
|
trig10(21) => read_fifo_we,
|
1489 |
|
|
trig10(22) => read_fifo_re,
|
1490 |
|
|
trig10(23) => rx_fifo_almost_empty,
|
1491 |
|
|
trig10(24) => HOLD_det_r,
|
1492 |
|
|
trig10(25) => ALIGN_det_r,
|
1493 |
|
|
trig10(26) => TWO_HOLD_det,
|
1494 |
|
|
trig10(27) => read_fifo_empty_i,
|
1495 |
|
|
trig10(28) => TWO_HOLD_det_r,
|
1496 |
|
|
trig10(29) => HOLD_det,
|
1497 |
|
|
trig10(30) => HOLD_stop_after_ALIGN_det,
|
1498 |
|
|
trig10(31) => ALIGN_det_r2,
|
1499 |
|
|
trig11 => dword_count,
|
1500 |
|
|
trig12 => rx_sector_count,
|
1501 |
|
|
trig13 => DATA_FIS_dword_count,
|
1502 |
|
|
trig14 => dword_count_value,
|
1503 |
|
|
trig15 => dword_count_init_value
|
1504 |
|
|
);
|
1505 |
|
|
|
1506 |
|
|
|
1507 |
|
|
SATA_TX_FRAME_ILA_i : sata_tx_frame_ila
|
1508 |
|
|
port map (
|
1509 |
|
|
control => sata_tx_frame_ila_control,
|
1510 |
|
|
clk => sata_user_clk,
|
1511 |
|
|
trig0 => tx_frame_value,
|
1512 |
|
|
trig1 => tx_dataout,
|
1513 |
|
|
trig2 => rx_datain,
|
1514 |
|
|
trig3 => tx_fifo_dout,
|
1515 |
|
|
trig4 => master_fsm_value,
|
1516 |
|
|
trig5 => tx_fifo_din,
|
1517 |
|
|
trig6 => write_fifo_din,
|
1518 |
|
|
trig7 => write_fifo_dout,
|
1519 |
|
|
trig8 => FIS_word_count,
|
1520 |
|
|
trig9 => scrambler_count,
|
1521 |
|
|
trig10(0) => tx_fifo_we,
|
1522 |
|
|
trig10(1) => tx_fifo_re,
|
1523 |
|
|
trig10(2) => tx_fifo_full,
|
1524 |
|
|
trig10(3) => align_en_out,
|
1525 |
|
|
trig10(4) => SYNC_det,
|
1526 |
|
|
trig10(5) => R_RDY_det,
|
1527 |
|
|
trig10(6) => R_IP_det,
|
1528 |
|
|
trig10(7) => R_OK_det,
|
1529 |
|
|
trig10(8) => R_ERR_det,
|
1530 |
|
|
trig10(9) => start_tx,
|
1531 |
|
|
trig10(10) => tx_done,
|
1532 |
|
|
trig10(11) => tx_fifo_almost_empty,
|
1533 |
|
|
trig10(12) => tx_charisk_out,
|
1534 |
|
|
trig10(13) => tx_fifo_empty,
|
1535 |
|
|
trig10(14) => scrambler_din_re,
|
1536 |
|
|
trig10(15) => ALIGN_det,
|
1537 |
|
|
trig10(16) => HOLD_start_det,
|
1538 |
|
|
trig10(17) => HOLD_stop_det,
|
1539 |
|
|
trig10(18) => CONT_det,
|
1540 |
|
|
trig10(19) => write_fifo_prog_full,
|
1541 |
|
|
trig10(20) => tx_err,
|
1542 |
|
|
trig10(21) => write_fifo_almost_empty,
|
1543 |
|
|
trig10(22) => new_cmd,
|
1544 |
|
|
trig10(23) => scrambler_reset_after_FIS,
|
1545 |
|
|
trig10(24) => write_fifo_we,
|
1546 |
|
|
trig10(25) => write_fifo_re,
|
1547 |
|
|
trig10(26) => write_fifo_empty,
|
1548 |
|
|
trig10(27) => scrambler_en,
|
1549 |
|
|
trig10(28) => tx_fifo_prog_full,
|
1550 |
|
|
trig10(29) => scrambler_count_en_data_fis,
|
1551 |
|
|
trig10(30) => scrambler_reset,
|
1552 |
|
|
trig10(31) => crc_en,
|
1553 |
|
|
trig11 => scrambler_din,
|
1554 |
|
|
trig12 => crc_dout,
|
1555 |
|
|
trig13 => tx_sector_count,
|
1556 |
|
|
trig14 => scrambler_count_value,
|
1557 |
|
|
trig15 => tx_fifo_data_count
|
1558 |
|
|
);
|
1559 |
|
|
|
1560 |
|
|
--trig14 => scrambler_count_init_value,
|
1561 |
|
|
end generate chipscope_gen_ila;
|
1562 |
|
|
|
1563 |
|
|
end BEHAV;
|