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ashwin_men |
-- Copyright (C) 2012
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-- Ashwin A. Mendon
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--
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-- This file is part of SATA2 core.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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----------------------------------------------------------------------------------------
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-- ENTITY: scrambler
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-- Version: 1.0
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-- Author: Ashwin Mendon
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-- Description: This sub-module implements the Scrambler Circuit for the SATA Protocol
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-- The code provides a parallel implementation of the following
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-- generator polynomial
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-- 16 15 13 4
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-- G(x) = x + x + x + x + 1
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-- The output of this scrambler is then XORed with the input data DWORD
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-- The scrambler is initialized to a value of 0xF0F6.
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-- The first DWORD output of the implementation is equal to 0xC2D2768D
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-- PORTS:
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-----------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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entity scrambler is
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generic(
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CHIPSCOPE : boolean := false
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);
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port(
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-- Clock and Reset Signals
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clk : in std_logic;
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reset : in std_logic;
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-- ChipScope ILA / Trigger Signals
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scrambler_ila_control : in std_logic_vector(35 downto 0);
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---------------------------------------
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-- Signals from/to Sata Link Layer
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scrambler_en : in std_logic;
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prim_scrambler : in std_logic;
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din_re : out std_logic;
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data_in : in std_logic_vector(0 to 31);
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data_out : out std_logic_vector(0 to 31);
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dout_we : out std_logic
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);
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end scrambler;
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-------------------------------------------------------------------------------
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-- ARCHITECTURE
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-------------------------------------------------------------------------------
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architecture BEHAV of scrambler is
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-------------------------------------------------------------------------------
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-- Constants
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-------------------------------------------------------------------------------
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constant SCRAMBLER_INIT : std_logic_vector(0 to 15) := x"F0F6";
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signal context : std_logic_vector (15 downto 0);
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signal context_next : std_logic_vector (31 downto 0);
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signal context_reg : std_logic_vector (31 downto 0);
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signal data_out_ila : std_logic_vector (31 downto 0);
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signal dout_we_reg : std_logic;
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signal dout_we_ila : std_logic;
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signal din_re_ila : std_logic;
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-----------------------------------------------------------------------------
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-- ILA Declaration
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-----------------------------------------------------------------------------
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component scrambler_ila
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port (
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control : in std_logic_vector(35 downto 0);
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clk : in std_logic;
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trig0 : in std_logic_vector(31 downto 0);
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trig1 : in std_logic_vector(31 downto 0);
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trig2 : in std_logic_vector(31 downto 0);
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trig3 : in std_logic_vector(31 downto 0);
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trig4 : in std_logic_vector(15 downto 0);
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trig5 : in std_logic_vector(3 downto 0)
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);
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end component;
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-------------------------------------------------------------------------------
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-- BEGIN
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-------------------------------------------------------------------------------
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begin
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-----------------------------------------------------------------------------
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-- PROCESS: SCRAMBLER_PROC
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-- PURPOSE: Registering Signals and Next State
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-----------------------------------------------------------------------------
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SCRAMBLER_PROC : process (clk)
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begin
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if ((clk'event) and (clk = '1')) then
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if (reset = '1') then
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--Initializing internal signals
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context <= SCRAMBLER_INIT;
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context_reg <= (others => '0');
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dout_we_reg <= '0';
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elsif (scrambler_en = '1') then
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-- Register all Current Signals to their _next Signals
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context <= context_next(31 downto 16);
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context_reg <= context_next;
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dout_we_reg <= '1';
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else
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context <= context;
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context_reg <= context_reg;
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dout_we_reg <= '0';
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end if;
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end if;
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end process SCRAMBLER_PROC ;
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context_next(31) <= context(12) xor context(10) xor context(7) xor context(3) xor context(1) xor context(0);
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context_next(30) <= context(15) xor context(14) xor context(12) xor context(11) xor context(9) xor context(6) xor context(3) xor context(2) xor context(0);
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context_next(29) <= context(15) xor context(13) xor context(12) xor context(11) xor context(10) xor context(8) xor context(5) xor context(3) xor context(2) xor context(1);
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context_next(28) <= context(14) xor context(12) xor context(11) xor context(10) xor context(9) xor context(7) xor context(4) xor context(2) xor context(1) xor context(0);
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context_next(27) <= context(15) xor context(14) xor context(13) xor context(12) xor context(11) xor context(10) xor context(9) xor context(8) xor context(6) xor context(1) xor context(0);
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context_next(26) <= context(15) xor context(13) xor context(11) xor context(10) xor context(9) xor context(8) xor context(7) xor context(5) xor context(3) xor context(0);
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context_next(25) <= context(15) xor context(10) xor context(9) xor context(8) xor context(7) xor context(6) xor context(4) xor context(3) xor context(2);
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context_next(24) <= context(14) xor context(9) xor context(8) xor context(7) xor context(6) xor context(5) xor context(3) xor context(2) xor context(1);
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context_next(23) <= context(13) xor context(8) xor context(7) xor context(6) xor context(5) xor context(4) xor context(2) xor context(1) xor context(0);
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context_next(22) <= context(15) xor context(14) xor context(7) xor context(6) xor context(5) xor context(4) xor context(1) xor context(0);
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context_next(21) <= context(15) xor context(13) xor context(12) xor context(6) xor context(5) xor context(4) xor context(0);
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context_next(20) <= context(15) xor context(11) xor context(5) xor context(4);
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context_next(19) <= context(14) xor context(10) xor context(4) xor context(3);
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context_next(18) <= context(13) xor context(9) xor context(3) xor context(2);
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context_next(17) <= context(12) xor context(8) xor context(2) xor context(1);
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context_next(16) <= context(11) xor context(7) xor context(1) xor context(0);
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context_next(15) <= context(15) xor context(14) xor context(12) xor context(10) xor context(6) xor context(3) xor context(0);
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context_next(14) <= context(15) xor context(13) xor context(12) xor context(11) xor context(9) xor context(5) xor context(3) xor context(2);
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context_next(13) <= context(14) xor context(12) xor context(11) xor context(10) xor context(8) xor context(4) xor context(2) xor context(1);
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context_next(12) <= context(13) xor context(11) xor context(10) xor context(9) xor context(7) xor context(3) xor context(1) xor context(0);
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context_next(11) <= context(15) xor context(14) xor context(10) xor context(9) xor context(8) xor context(6) xor context(3) xor context(2) xor context(0);
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context_next(10) <= context(15) xor context(13) xor context(12) xor context(9) xor context(8) xor context(7) xor context(5) xor context(3) xor context(2) xor context(1);
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context_next(9) <= context(14) xor context(12) xor context(11) xor context(8) xor context(7) xor context(6) xor context(4) xor context(2) xor context(1) xor context(0);
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context_next(8) <= context(15) xor context(14) xor context(13) xor context(12) xor context(11) xor context(10) xor context(7) xor context(6) xor context(5) xor context(1) xor context(0);
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context_next(7) <= context(15) xor context(13) xor context(11) xor context(10) xor context(9) xor context(6) xor context(5) xor context(4) xor context(3) xor context(0);
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context_next(6) <= context(15) xor context(10) xor context(9) xor context(8) xor context(5) xor context(4) xor context(2);
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context_next(5) <= context(14) xor context(9) xor context(8) xor context(7) xor context(4) xor context(3) xor context(1);
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context_next(4) <= context(13) xor context(8) xor context(7) xor context(6) xor context(3) xor context(2) xor context(0);
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context_next(3) <= context(15) xor context(14) xor context(7) xor context(6) xor context(5) xor context(3) xor context(2) xor context(1);
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context_next(2) <= context(14) xor context(13) xor context(6) xor context(5) xor context(4) xor context(2) xor context(1) xor context(0);
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context_next(1) <= context(15) xor context(14) xor context(13) xor context(5) xor context(4) xor context(1) xor context(0);
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context_next(0) <= context(15) xor context(13) xor context(4) xor context(0);
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data_out_ila <= (context_reg xor data_in) when prim_scrambler = '0' else (context_reg);
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--dout_we_ila <= dout_we_reg when scrambler_en = '1' else '0';
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dout_we_ila <= dout_we_reg;
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din_re_ila <= '1' when scrambler_en = '1' else '0';
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-----------------------------------------------------------------------------
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-- ILA Instantiation
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-----------------------------------------------------------------------------
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data_out <= data_out_ila;
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dout_we <= dout_we_ila;
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din_re <= din_re_ila;
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chipscope_gen_ila : if (CHIPSCOPE) generate
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SCRAMBLER_ILA_i : scrambler_ila
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port map (
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control => scrambler_ila_control,
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clk => clk,
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trig0 => data_in,
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trig1 => data_out_ila,
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trig2 => context_reg,
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trig3 => context_next,
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trig4 => context,
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trig5(0) => scrambler_en,
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trig5(1) => din_re_ila,
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trig5(2) => dout_we_ila,
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trig5(3) => reset
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);
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end generate chipscope_gen_ila;
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end BEHAV;
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