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Subversion Repositories sata_controller_core

[/] [sata_controller_core/] [trunk/] [sata2_fifo_v1_00_a/] [netlist/] [coregen.cgp] - Blame information for rev 17

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Line No. Rev Author Line
1 2 ashwin_men 
SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = VHDL
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SET device = xc6vlx240t
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SET devicefamily = virtex6
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SET flowvendor = Other
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = ff1156
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -1
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SET verilogsim = false
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SET vhdlsim = true
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SET workingdirectory = ./tmp/
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