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URL https://opencores.org/ocsvn/sata_controller_core/sata_controller_core/trunk

Subversion Repositories sata_controller_core

[/] [sata_controller_core/] [trunk/] [sata2_fifo_v1_00_a/] [syn/] [sata_core.prj] - Blame information for rev 17

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Line No. Rev Author Line
1 2 ashwin_men 
verilog work "../hdl/verilog/sata_gtx.v"
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verilog work "../hdl/verilog/sata_gtx_dual.v"
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verilog work "../hdl/verilog/mgt_usrclk_source_mmcm.v"
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verilog work "../hdl/verilog/mux_21.v"
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verilog work "../hdl/verilog/mux_41.v"
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verilog work "../hdl/verilog/oob_control.v"
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verilog work "../hdl/verilog/sata_phy.v"
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vhdl work ../hdl/vhdl/mux_161.vhd
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vhdl work ../hdl/vhdl/crc.vhd
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vhdl work ../hdl/vhdl/scrambler.vhd
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vhdl work ../hdl/vhdl/sata_link_layer.vhd
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vhdl work ../hdl/vhdl/command_layer.vhd
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vhdl work ../hdl/vhdl/sata_core.vhd

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