URL https://opencores.org/ocsvn/sata_phy/sata_phy/trunk

Subversion Repositories sata_phy

[/] [sata_phy/] [trunk/] [hdl/] [det_pos_edge.v] - Blame information for rev 7

Line No.	Rev	Author	Line
1	7	beandigita	`////////////////////////////////////////////////////////////`
2			`//`
3			`// This confidential and proprietary software may be used`
4			`// only as authorized by a licensing agreement from`
5			`// Bean Digital Ltd`
6			`// In the event of publication, the following notice is`
7			`// applicable:`
8			`//`
9			`// (C)COPYRIGHT 2009 BEAN DIGITAL LTD.`
10			`// ALL RIGHTS RESERVED`
11			`//`
12			`// The entire notice above must be reproduced on all`
13			`// authorized copies.`
14			`//`
15			`// File : det_pos_edge.v`
16			`// Author : J.Bean`
17			`// Date : Nov 2009`
18			`// Description : Detect a positive edge.`
19			`////////////////////////////////////////////////////////////`
20
21			`resetall
22			`timescale 1ns/10ps
23
24			`module det_pos_edge(`
25			`input wire clk,`
26			`input wire rst_n,`
27			`input wire d,`
28			`output wire q`
29			`);`
30
31			`////////////////////////////////////////////////////////////`
32			`// Signals`
33			`////////////////////////////////////////////////////////////`
34
35			`reg d_p1;`
36
37			`////////////////////////////////////////////////////////////`
38			`// Comb Assign : Q`
39			`// Description :`
40			`////////////////////////////////////////////////////////////`
41
42			`assign q = d & ~d_p1;`
43
44			`////////////////////////////////////////////////////////////`
45			`// Seq Block : Data pipeline`
46			`// Description :`
47			`////////////////////////////////////////////////////////////`
48
49			`always @(negedge rst_n or posedge clk)`
50			`begin`
51			`if (rst_n == 0) begin`
52			`d_p1 <= 0;`
53			`end else begin`
54			`d_p1 <= d;`
55			`end`
56			`end`
57
58			`endmodule`