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[/] [sata_phy/] [trunk/] [hdl/] [mux.v] - Blame information for rev 9

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1 9 beandigita
////////////////////////////////////////////////////////////
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//
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// This confidential and proprietary software may be used
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// only as authorized by a licensing agreement from
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// Bean Digital Ltd
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// In the event of publication, the following notice is
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// applicable:
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//
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// (C)COPYRIGHT 2009 BEAN DIGITAL LTD.
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// ALL RIGHTS RESERVED
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//
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// The entire notice above must be reproduced on all
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// authorized copies.
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//
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// File        : mux.v
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// Author      : J.Bean
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// Date        : Sep 2009
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// Description : Multiplexer
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////////////////////////////////////////////////////////////
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`resetall
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`timescale 1ns/10ps
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module mux
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  #(parameter DATA_BITS  = 16,                // Data bits
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    parameter IP_NUM     = 4,                 // Number of inputs
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    parameter USE_OP_REG = 0)(                // Enable Register on Output 
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  input  wire                        clk,     // Clock
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  input  wire [IP_NUM*DATA_BITS-1:0] data_i,  // Data Input
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  input  wire [7:0]                  sel_i,   // Input Select
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  output wire [DATA_BITS-1:0]        data_o   // Data Output
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);
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////////////////////////////////////////////////////////////
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// Signals
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//////////////////////////////////////////////////////////// 
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genvar i;
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reg  [DATA_BITS-1:0] ip_array [0:IP_NUM-1];
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wire [DATA_BITS-1:0] data_c;
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reg  [DATA_BITS-1:0] data_r;
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////////////////////////////////////////////////////////////
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// Comb Assign : Data Output
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// Description : 
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////////////////////////////////////////////////////////////
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assign data_o = (USE_OP_REG == 1) ? data_r : data_c;
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////////////////////////////////////////////////////////////
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// Comb Assign : Data Comb
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// Description : Assign an input vector from the array.
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////////////////////////////////////////////////////////////
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assign data_c = ip_array[sel_i];
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////////////////////////////////////////////////////////////
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// Generate    : Input array
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// Description : Create an array of input vectors.
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////////////////////////////////////////////////////////////
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generate
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  for(i=0; i<IP_NUM; i=i+1) begin: mux_gen
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    always @(*)
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    begin
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      ip_array[i] = data_i[(i+1)*DATA_BITS-1:i*DATA_BITS];
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    end
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  end
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endgenerate
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////////////////////////////////////////////////////////////
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// Seq Block   : Data Registered
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// Description : 
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// Assign an input vector from the array.
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////////////////////////////////////////////////////////////
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always @(posedge clk)
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begin
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  data_r <= ip_array[sel_i];
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end
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endmodule

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