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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version : 1.11
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// \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
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// / / Filename : sata_s6_sata1_gtp.v
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// /___/ /\
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// \ \ / \
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// \___\/\___\
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//
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//
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// Module sata_s6_sata1_gtp (a GTP Wrapper)
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// Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
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//
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//
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// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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`timescale 1ns / 1ps
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//***************************** Entity Declaration ****************************
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(* CORE_GENERATION_INFO = "sata_s6_sata1_gtp,s6_gtpwizard_v1_11,{gtp0_protocol_file=sata,gtp1_protocol_file=Use_GTP0_settings}" *)
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module sata_s6_sata1_gtp #
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(
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// Simulation attributes
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parameter WRAPPER_SIM_GTPRESET_SPEEDUP = 0, // Set to 1 to speed up sim reset
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parameter WRAPPER_CLK25_DIVIDER_0 = 6,
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parameter WRAPPER_CLK25_DIVIDER_1 = 6,
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parameter WRAPPER_PLL_DIVSEL_FB_0 = 2,
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parameter WRAPPER_PLL_DIVSEL_FB_1 = 2,
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parameter WRAPPER_PLL_DIVSEL_REF_0 = 1,
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parameter WRAPPER_PLL_DIVSEL_REF_1 = 1,
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parameter WRAPPER_SIMULATION = 0 // Set to 1 for simulation
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)
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(
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//_________________________________________________________________________
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//_________________________________________________________________________
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//TILE0 (X0_Y0)
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//---------------------- Loopback and Powerdown Ports ----------------------
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input [2:0] TILE0_LOOPBACK0_IN,
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input [2:0] TILE0_LOOPBACK1_IN,
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//------------------------------- PLL Ports --------------------------------
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input TILE0_CLK00_IN,
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input TILE0_CLK01_IN,
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input TILE0_GTPRESET0_IN,
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input TILE0_GTPRESET1_IN,
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output TILE0_PLLLKDET0_OUT,
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output TILE0_RESETDONE0_OUT,
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output TILE0_RESETDONE1_OUT,
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//--------------------- Receive Ports - 8b10b Decoder ----------------------
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output [1:0] TILE0_RXCHARISCOMMA0_OUT,
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output [1:0] TILE0_RXCHARISCOMMA1_OUT,
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output [1:0] TILE0_RXCHARISK0_OUT,
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output [1:0] TILE0_RXCHARISK1_OUT,
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output [1:0] TILE0_RXDISPERR0_OUT,
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output [1:0] TILE0_RXDISPERR1_OUT,
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output [1:0] TILE0_RXNOTINTABLE0_OUT,
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output [1:0] TILE0_RXNOTINTABLE1_OUT,
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//-------------------- Receive Ports - Clock Correction --------------------
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output [2:0] TILE0_RXCLKCORCNT0_OUT,
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output [2:0] TILE0_RXCLKCORCNT1_OUT,
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//------------- Receive Ports - Comma Detection and Alignment --------------
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output TILE0_RXBYTEISALIGNED0_OUT,
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output TILE0_RXBYTEISALIGNED1_OUT,
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input TILE0_RXENMCOMMAALIGN0_IN,
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input TILE0_RXENMCOMMAALIGN1_IN,
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input TILE0_RXENPCOMMAALIGN0_IN,
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input TILE0_RXENPCOMMAALIGN1_IN,
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//----------------- Receive Ports - RX Data Path interface -----------------
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output [15:0] TILE0_RXDATA0_OUT,
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output [15:0] TILE0_RXDATA1_OUT,
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output TILE0_RXRECCLK0_OUT,
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output TILE0_RXRECCLK1_OUT,
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input TILE0_RXRESET0_IN,
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input TILE0_RXRESET1_IN,
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input TILE0_RXUSRCLK0_IN,
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input TILE0_RXUSRCLK1_IN,
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input TILE0_RXUSRCLK20_IN,
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input TILE0_RXUSRCLK21_IN,
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//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
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input TILE0_GATERXELECIDLE0_IN,
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input TILE0_GATERXELECIDLE1_IN,
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input TILE0_IGNORESIGDET0_IN,
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input TILE0_IGNORESIGDET1_IN,
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output TILE0_RXELECIDLE0_OUT,
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output TILE0_RXELECIDLE1_OUT,
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input [1:0] TILE0_RXEQMIX0_IN,
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input [1:0] TILE0_RXEQMIX1_IN,
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input TILE0_RXN0_IN,
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input TILE0_RXN1_IN,
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input TILE0_RXP0_IN,
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input TILE0_RXP1_IN,
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//--------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
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output [2:0] TILE0_RXSTATUS0_OUT,
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output [2:0] TILE0_RXSTATUS1_OUT,
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//-------------------------- TX/RX Datapath Ports --------------------------
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output [1:0] TILE0_GTPCLKOUT0_OUT,
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output [1:0] TILE0_GTPCLKOUT1_OUT,
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//----------------- Transmit Ports - 8b10b Encoder Control -----------------
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input [1:0] TILE0_TXCHARISK0_IN,
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input [1:0] TILE0_TXCHARISK1_IN,
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//---------------- Transmit Ports - TX Data Path interface -----------------
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input [15:0] TILE0_TXDATA0_IN,
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input [15:0] TILE0_TXDATA1_IN,
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output TILE0_TXOUTCLK0_OUT,
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output TILE0_TXOUTCLK1_OUT,
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input TILE0_TXRESET0_IN,
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input TILE0_TXRESET1_IN,
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input TILE0_TXUSRCLK0_IN,
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input TILE0_TXUSRCLK1_IN,
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input TILE0_TXUSRCLK20_IN,
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input TILE0_TXUSRCLK21_IN,
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//------------- Transmit Ports - TX Driver and OOB signalling --------------
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input [3:0] TILE0_TXDIFFCTRL0_IN,
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input [3:0] TILE0_TXDIFFCTRL1_IN,
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output TILE0_TXN0_OUT,
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output TILE0_TXN1_OUT,
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output TILE0_TXP0_OUT,
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output TILE0_TXP1_OUT,
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input [2:0] TILE0_TXPREEMPHASIS0_IN,
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input [2:0] TILE0_TXPREEMPHASIS1_IN,
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//--------------- Transmit Ports - TX Ports for PCI Express ----------------
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input TILE0_TXELECIDLE0_IN,
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input TILE0_TXELECIDLE1_IN,
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//------------------- Transmit Ports - TX Ports for SATA -------------------
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input TILE0_TXCOMSTART0_IN,
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input TILE0_TXCOMSTART1_IN,
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input TILE0_TXCOMTYPE0_IN,
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input TILE0_TXCOMTYPE1_IN
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);
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//***************************** Wire Declarations *****************************
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// ground and vcc signals
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wire tied_to_ground_i;
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wire [63:0] tied_to_ground_vec_i;
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wire tied_to_vcc_i;
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wire [63:0] tied_to_vcc_vec_i;
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wire tile0_plllkdet0_i;
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wire tile0_plllkdet1_i;
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reg tile0_plllkdet0_i2;
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reg [4:0] count00;
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reg start00;
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//********************************* Main Body of Code**************************
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assign tied_to_ground_i = 1'b0;
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assign tied_to_ground_vec_i = 64'h0000000000000000;
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assign tied_to_vcc_i = 1'b1;
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assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
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generate
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if (WRAPPER_SIMULATION==1)
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begin : simulation
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assign TILE0_PLLLKDET0_OUT = tile0_plllkdet0_i2;
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always@(posedge TILE0_CLK00_IN or posedge TILE0_GTPRESET0_IN)
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begin
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if (TILE0_GTPRESET0_IN == 1'b1) begin
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count00 <= 5'b00000;
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end
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else begin
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if ((count00 == 5'b10100) | (tile0_plllkdet0_i == 1'b0)) begin
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count00 <= 5'b00000;
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end
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else begin
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count00 <= count00 + 5'b00001;
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end
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end
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end
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always@(posedge TILE0_CLK00_IN or negedge tile0_plllkdet0_i)
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begin
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if(tile0_plllkdet0_i == 1'b0) begin
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tile0_plllkdet0_i2 <= 1'b0;
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end
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else begin
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if((count00 == 5'b10100) & (tile0_plllkdet0_i == 1'b1)) begin
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tile0_plllkdet0_i2 <= 1'b1;
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end
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end
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end
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end //end WRAPPER_SIMULATION =1 generate section
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else
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begin: implementation
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assign TILE0_PLLLKDET0_OUT = tile0_plllkdet0_i;
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end
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endgenerate //End generate for WRAPPER_SIMULATION
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//------------------------- Tile Instances -------------------------------
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//_________________________________________________________________________
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//_________________________________________________________________________
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//TILE0 (X0_Y0)
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sata_s6_sata1_gtp_tile #
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(
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// Simulation attributes
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.TILE_SIM_GTPRESET_SPEEDUP (WRAPPER_SIM_GTPRESET_SPEEDUP),
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.TILE_CLK25_DIVIDER_0 (WRAPPER_CLK25_DIVIDER_0),
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.TILE_CLK25_DIVIDER_1 (WRAPPER_CLK25_DIVIDER_1),
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.TILE_PLL_DIVSEL_FB_0 (WRAPPER_PLL_DIVSEL_FB_0),
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.TILE_PLL_DIVSEL_FB_1 (WRAPPER_PLL_DIVSEL_FB_1),
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.TILE_PLL_DIVSEL_REF_0 (WRAPPER_PLL_DIVSEL_REF_0),
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.TILE_PLL_DIVSEL_REF_1 (WRAPPER_PLL_DIVSEL_REF_1),
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//
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.TILE_PLL_SOURCE_0 ("PLL0"),
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.TILE_PLL_SOURCE_1 ("PLL0")
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)
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tile0_sata_s6_sata1_gtp_i
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(
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//---------------------- Loopback and Powerdown Ports ----------------------
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.LOOPBACK0_IN (TILE0_LOOPBACK0_IN),
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.LOOPBACK1_IN (TILE0_LOOPBACK1_IN),
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//------------------------------- PLL Ports --------------------------------
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.CLK00_IN (TILE0_CLK00_IN),
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.CLK01_IN (TILE0_CLK01_IN),
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.GTPRESET0_IN (TILE0_GTPRESET0_IN),
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.GTPRESET1_IN (TILE0_GTPRESET1_IN),
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.PLLLKDET0_OUT (tile0_plllkdet0_i),
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.PLLLKDET1_OUT (tile0_plllkdet1_i),
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.RESETDONE0_OUT (TILE0_RESETDONE0_OUT),
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.RESETDONE1_OUT (TILE0_RESETDONE1_OUT),
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//--------------------- Receive Ports - 8b10b Decoder ----------------------
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.RXCHARISCOMMA0_OUT (TILE0_RXCHARISCOMMA0_OUT),
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.RXCHARISCOMMA1_OUT (TILE0_RXCHARISCOMMA1_OUT),
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.RXCHARISK0_OUT (TILE0_RXCHARISK0_OUT),
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.RXCHARISK1_OUT (TILE0_RXCHARISK1_OUT),
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.RXDISPERR0_OUT (TILE0_RXDISPERR0_OUT),
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.RXDISPERR1_OUT (TILE0_RXDISPERR1_OUT),
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.RXNOTINTABLE0_OUT (TILE0_RXNOTINTABLE0_OUT),
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.RXNOTINTABLE1_OUT (TILE0_RXNOTINTABLE1_OUT),
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//-------------------- Receive Ports - Clock Correction --------------------
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.RXCLKCORCNT0_OUT (TILE0_RXCLKCORCNT0_OUT),
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.RXCLKCORCNT1_OUT (TILE0_RXCLKCORCNT1_OUT),
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//------------- Receive Ports - Comma Detection and Alignment --------------
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.RXBYTEISALIGNED0_OUT (TILE0_RXBYTEISALIGNED0_OUT),
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.RXBYTEISALIGNED1_OUT (TILE0_RXBYTEISALIGNED1_OUT),
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.RXENMCOMMAALIGN0_IN (TILE0_RXENMCOMMAALIGN0_IN),
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.RXENMCOMMAALIGN1_IN (TILE0_RXENMCOMMAALIGN1_IN),
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.RXENPCOMMAALIGN0_IN (TILE0_RXENPCOMMAALIGN0_IN),
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.RXENPCOMMAALIGN1_IN (TILE0_RXENPCOMMAALIGN1_IN),
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//----------------- Receive Ports - RX Data Path interface -----------------
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|
|
.RXDATA0_OUT (TILE0_RXDATA0_OUT),
|
313 |
|
|
.RXDATA1_OUT (TILE0_RXDATA1_OUT),
|
314 |
|
|
.RXRECCLK0_OUT (TILE0_RXRECCLK0_OUT),
|
315 |
|
|
.RXRECCLK1_OUT (TILE0_RXRECCLK1_OUT),
|
316 |
|
|
.RXRESET0_IN (TILE0_RXRESET0_IN),
|
317 |
|
|
.RXRESET1_IN (TILE0_RXRESET1_IN),
|
318 |
|
|
.RXUSRCLK0_IN (TILE0_RXUSRCLK0_IN),
|
319 |
|
|
.RXUSRCLK1_IN (TILE0_RXUSRCLK1_IN),
|
320 |
|
|
.RXUSRCLK20_IN (TILE0_RXUSRCLK20_IN),
|
321 |
|
|
.RXUSRCLK21_IN (TILE0_RXUSRCLK21_IN),
|
322 |
|
|
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
|
323 |
|
|
.GATERXELECIDLE0_IN (TILE0_GATERXELECIDLE0_IN),
|
324 |
|
|
.GATERXELECIDLE1_IN (TILE0_GATERXELECIDLE1_IN),
|
325 |
|
|
.IGNORESIGDET0_IN (TILE0_IGNORESIGDET0_IN),
|
326 |
|
|
.IGNORESIGDET1_IN (TILE0_IGNORESIGDET1_IN),
|
327 |
|
|
.RXELECIDLE0_OUT (TILE0_RXELECIDLE0_OUT),
|
328 |
|
|
.RXELECIDLE1_OUT (TILE0_RXELECIDLE1_OUT),
|
329 |
|
|
.RXEQMIX0_IN (TILE0_RXEQMIX0_IN),
|
330 |
|
|
.RXEQMIX1_IN (TILE0_RXEQMIX1_IN),
|
331 |
|
|
.RXN0_IN (TILE0_RXN0_IN),
|
332 |
|
|
.RXN1_IN (TILE0_RXN1_IN),
|
333 |
|
|
.RXP0_IN (TILE0_RXP0_IN),
|
334 |
|
|
.RXP1_IN (TILE0_RXP1_IN),
|
335 |
|
|
//--------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
|
336 |
|
|
.RXSTATUS0_OUT (TILE0_RXSTATUS0_OUT),
|
337 |
|
|
.RXSTATUS1_OUT (TILE0_RXSTATUS1_OUT),
|
338 |
|
|
//-------------------------- TX/RX Datapath Ports --------------------------
|
339 |
|
|
.GTPCLKOUT0_OUT (TILE0_GTPCLKOUT0_OUT),
|
340 |
|
|
.GTPCLKOUT1_OUT (TILE0_GTPCLKOUT1_OUT),
|
341 |
|
|
//----------------- Transmit Ports - 8b10b Encoder Control -----------------
|
342 |
|
|
.TXCHARISK0_IN (TILE0_TXCHARISK0_IN),
|
343 |
|
|
.TXCHARISK1_IN (TILE0_TXCHARISK1_IN),
|
344 |
|
|
//---------------- Transmit Ports - TX Data Path interface -----------------
|
345 |
|
|
.TXDATA0_IN (TILE0_TXDATA0_IN),
|
346 |
|
|
.TXDATA1_IN (TILE0_TXDATA1_IN),
|
347 |
|
|
.TXOUTCLK0_OUT (TILE0_TXOUTCLK0_OUT),
|
348 |
|
|
.TXOUTCLK1_OUT (TILE0_TXOUTCLK1_OUT),
|
349 |
|
|
.TXRESET0_IN (TILE0_TXRESET0_IN),
|
350 |
|
|
.TXRESET1_IN (TILE0_TXRESET1_IN),
|
351 |
|
|
.TXUSRCLK0_IN (TILE0_TXUSRCLK0_IN),
|
352 |
|
|
.TXUSRCLK1_IN (TILE0_TXUSRCLK1_IN),
|
353 |
|
|
.TXUSRCLK20_IN (TILE0_TXUSRCLK20_IN),
|
354 |
|
|
.TXUSRCLK21_IN (TILE0_TXUSRCLK21_IN),
|
355 |
|
|
//------------- Transmit Ports - TX Driver and OOB signalling --------------
|
356 |
|
|
.TXDIFFCTRL0_IN (TILE0_TXDIFFCTRL0_IN),
|
357 |
|
|
.TXDIFFCTRL1_IN (TILE0_TXDIFFCTRL1_IN),
|
358 |
|
|
.TXN0_OUT (TILE0_TXN0_OUT),
|
359 |
|
|
.TXN1_OUT (TILE0_TXN1_OUT),
|
360 |
|
|
.TXP0_OUT (TILE0_TXP0_OUT),
|
361 |
|
|
.TXP1_OUT (TILE0_TXP1_OUT),
|
362 |
|
|
.TXPREEMPHASIS0_IN (TILE0_TXPREEMPHASIS0_IN),
|
363 |
|
|
.TXPREEMPHASIS1_IN (TILE0_TXPREEMPHASIS1_IN),
|
364 |
|
|
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
|
365 |
|
|
.TXELECIDLE0_IN (TILE0_TXELECIDLE0_IN),
|
366 |
|
|
.TXELECIDLE1_IN (TILE0_TXELECIDLE1_IN),
|
367 |
|
|
//------------------- Transmit Ports - TX Ports for SATA -------------------
|
368 |
|
|
.TXCOMSTART0_IN (TILE0_TXCOMSTART0_IN),
|
369 |
|
|
.TXCOMSTART1_IN (TILE0_TXCOMSTART1_IN),
|
370 |
|
|
.TXCOMTYPE0_IN (TILE0_TXCOMTYPE0_IN),
|
371 |
|
|
.TXCOMTYPE1_IN (TILE0_TXCOMTYPE1_IN)
|
372 |
|
|
|
373 |
|
|
);
|
374 |
|
|
|
375 |
|
|
|
376 |
|
|
|
377 |
|
|
endmodule
|
378 |
|
|
|