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DavidRAMBA |
--=============================================================================
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-- TITRE : TOP_FPGACONC
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-- DESCRIPTION :
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-- Module TOP du FPGA du COncentrateur
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-- FICHIER : top_fpgaconc.vhd
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--=============================================================================
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-- CREATION
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-- DATE AUTEUR PROJET REVISION
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-- 10/04/2012 DRA CONCERTO V1.0
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--=============================================================================
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-- HISTORIQUE DES MODIFICATIONS :
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-- DATE AUTEUR PROJET REVISION
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--=============================================================================
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_ARITH.ALL;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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USE STD.TEXTIO.all;
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USE IEEE.STD_LOGIC_TEXTIO.ALL;
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LIBRARY UNISIM;
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USE UNISIM.VComponents.ALL;
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LIBRARY work;
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USE work.package_saturn.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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ENTITY simu_fpgacosil2_tb IS
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END simu_fpgacosil2_tb;
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ARCHITECTURE rtl of simu_fpgacosil2_tb is
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-- signaux utilisés pour les fonctions systèmes
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SIGNAL clk_96 : STD_LOGIC:= '0'; -- Pour récupérer l'horloge CLKx2 à la sortie du DCM
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SIGNAL clk_pcie : STD_LOGIC:= '0'; -- Horloge à 62.5 MHz issue de l'I/F PCIe
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SIGNAL rst96_n : STD_LOGIC:= '0'; -- reset resynchronisé sur clk96
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SIGNAL rstpcie_n : STD_LOGIC := '0'; -- Pour filtrer le reset entrant
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SIGNAL iid : STD_LOGIC_VECTOR(63 DOWNTO 0) := x"0123456789ABCDEF";
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-- Signaux d'interface entre le module de comm et le module spi PIC
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SIGNAL tid : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL cpy1 : STD_LOGIC;
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SIGNAL cpy2 : STD_LOGIC;
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SIGNAL repli : STD_LOGIC;
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SIGNAL topcyc : STD_LOGIC;
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SIGNAL l7_rx1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL l7_soc1 : STD_LOGIC;
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SIGNAL l7_rd1 : STD_LOGIC;
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SIGNAL l7_comdispo1: STD_LOGIC;
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SIGNAL l7_newframe1: STD_LOGIC;
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SIGNAL l7_l2ok1 : STD_LOGIC;
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SIGNAL l7_overflow1: STD_LOGIC;
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SIGNAL l7_rx2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL l7_soc2 : STD_LOGIC;
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SIGNAL l7_rd2 : STD_LOGIC;
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SIGNAL l7_comdispo2: STD_LOGIC;
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SIGNAL l7_newframe2: STD_LOGIC;
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SIGNAL l7_l2ok2 : STD_LOGIC;
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SIGNAL l7_overflow2: STD_LOGIC;
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SIGNAL tx_dat : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL val_txdat : STD_LOGIC;
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SIGNAL tx_sof : STD_LOGIC;
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SIGNAL tx_eof : STD_LOGIC;
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SIGNAL txdat_free : STD_LOGIC;
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SIGNAL clr_fifo_tx : STD_LOGIC;
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-- Signaux du bus local de l'interface PCIe
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SIGNAL rd_addr : STD_LOGIC_VECTOR(NBBIT_ADD_LOCAL-1 downto 0); -- Bus d'@ en lecture
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SIGNAL rd_data : STD_LOGIC_VECTOR(31 downto 0); -- Données lues sur le bus local
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SIGNAL rd_be : STD_LOGIC_VECTOR(3 downto 0); -- Byte Enable en lecture
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SIGNAL rd_en : STD_LOGIC; -- Signal d'ordre de lecture
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SIGNAL wr_addr : STD_LOGIC_VECTOR(NBBIT_ADD_LOCAL-1 downto 0); -- Bus d'@ en écriture
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SIGNAL wr_data : STD_LOGIC_VECTOR(31 downto 0); -- Données à écrire sur le bus local
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SIGNAL wr_be : STD_LOGIC_VECTOR(3 downto 0); -- Byte enable en écriture
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SIGNAL wr_en : STD_LOGIC; -- Signal d'ordre d'écriture
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SIGNAL wr_busy : STD_LOGIC; -- Indique que le bus local est occupé en écriture
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SIGNAL link_up_n : STD_LOGIC; -- Indique le lien PCIe est étali avec le host
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SIGNAL dma_req : STD_LOGIC; -- Requête d'un DMA
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SIGNAL dma_add_dest : STD_LOGIC_VECTOR(31 downto 0); -- Adresse de estination (coté PC) pour le DMA
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SIGNAL dma_compl : STD_LOGIC; -- Indique le DMA est fini
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SIGNAL dma_read : STD_LOGIC; -- Ordre de lecture pour fetcher une donnée supplémentaire à envoyer par DMA
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SIGNAL dma_ack : STD_LOGIC; -- Indique que la demande de DMA est acceptée
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SIGNAL dma_size : STD_LOGIC_VECTOR(7 downto 0); -- Nombre de mots de 32 bits à tansférer par DMA
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SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); -- Données à transmettre par DMA (fetchée par dma_read)
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SIGNAL dma_timestamp : STD_LOGIC_VECTOR(7 DOWNTO 0);
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-- Signaux de gestion du module memory_map
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SIGNAL rst_regn : STD_LOGIC; -- Reset interne piloté par registre
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SIGNAL actif : STD_LOGIC; -- Indique que le concentrateur est actif
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SIGNAL store_enable : STD_LOGIC; -- Autorise le transfert DMA des trames incidentes
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SIGNAL rx_flushn : STD_LOGIC;
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SIGNAL dma_inprogress : STD_LOGIC; -- A 1 tant que le module DMA est en cours de transfert
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SIGNAL update_ena : STD_LOGIC; -- Autorise la mise à jour de la mémoire TX_PER
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SIGNAL baudrate : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Code du baudrate de communication (entre 50Kbits et 12MBits)
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SIGNAL tx_ena_periodic: STD_LOGIC_VECTOR(31 DOWNTO 0);-- Autorisation à émettre d'une zone périodique
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SIGNAL tx_ena_aper : STD_LOGIC_VECTOR(31 DOWNTO 0);-- Autorisation à émettre d'une zone apériodique
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SIGNAL clr_txena_aper : STD_LOGIC_VECTOR(31 DOWNTO 0);-- Ordre de remise à 0 d'une zone de transmission apériodique
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SIGNAL dma_base_pa : STD_LOGIC_VECTOR(31 DOWNTO 0);-- Adresse physique de base pour les DMA (coté PC)
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SIGNAL bufferrx1_full : STD_LOGIC_VECTOR(31 DOWNTO 0);-- Indique les zones de stockages des trames Rx1 encore pleines
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SIGNAL bufferrx2_full : STD_LOGIC_VECTOR(31 DOWNTO 0);-- Indique les zones de stockages des trames Rx2 encore pleines
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SIGNAL buffertx_full : STD_LOGIC_VECTOR(31 DOWNTO 0);-- Indique les zones de stockages des trames Tx encore pleines
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SIGNAL newframe_rx1 : STD_LOGIC_VECTOR(31 DOWNTO 0);-- Indique la zone de stockage d'une nouvelle trame Rx1
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SIGNAL newframe_rx2 : STD_LOGIC_VECTOR(31 DOWNTO 0);-- Indique la zone de stockage d'une nouvelle trame Rx2
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SIGNAL newframe_tx : STD_LOGIC_VECTOR(31 DOWNTO 0);-- Indique la zone de stockage d'une nouvelle trame Tx
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SIGNAL rx1_overflow : STD_LOGIC; -- Indique la perte d'une trame sur RX1 faute de place en mémoire
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SIGNAL rx2_overflow : STD_LOGIC; -- Indique la perte d'une trame sur RX2 faute de place en mémoire
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SIGNAL tx_overflow : STD_LOGIC; -- Indique la perte d'une trame sur TX faute de place en mémoire
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SIGNAL rx1_badformat : STD_LOGIC; -- Indique une trame reçue avec un mauvais format ou mauvais CRC sur Rx1
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SIGNAL rx2_badformat : STD_LOGIC; -- Indique une trame reçue avec un mauvais format ou mauvais CRC sur Rx2
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SIGNAL addrr_tx : STD_LOGIC_VECTOR(14 DOWNTO 0);-- @ de lecture des zones TXAPER et TXPER
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SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Données lues dans les zones TXAPER et TXPER
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SIGNAL rd_datatx : STD_LOGIC; -- Signal de lecture dans une res mémoire APER ou PER
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-- Signaux du flux de données entrant sur les LS pour envoyer vers PCIe synchrone de clk_96
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SIGNAL data_storerx1 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Données à stocker en mémoire avant DMA
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SIGNAL val_storerx1 : STD_LOGIC; -- Validant du bus data_store(signal write)
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SIGNAL sof_storerx1 : STD_LOGIC; -- Indique un début de trame (nouvelle trame). Synchrone du 1er octet envoyé
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SIGNAL eof_storerx1 : STD_LOGIC; -- Indique que la trame est finie (plus de données à envoyer)
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SIGNAL crcok_storerx1 : STD_LOGIC; -- Indique que le CRC et le format est bon (sycnhrone de eof)
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SIGNAL data_storerx2 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem pour RX2
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SIGNAL val_storerx2 : STD_LOGIC;
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SIGNAL sof_storerx2 : STD_LOGIC;
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SIGNAL eof_storerx2 : STD_LOGIC;
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SIGNAL crcok_storerx2 : STD_LOGIC;
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SIGNAL tx_val : STD_LOGIC; -- Pour valider les données Tx vers le PCIe
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-- Signaux du flux de données entrant sur les LS pour envoyer vers PCIe synchrone de clk_pcie
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SIGNAL data_pcie_rx1 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Données à stocker en mémoire avant DMA
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SIGNAL val_pcie_rx1 : STD_LOGIC; -- Validant du bus data_store(signal write)
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SIGNAL sof_pcie_rx1 : STD_LOGIC; -- Indique un début de trame (nouvelle trame). Synchrone du 1er octet envoyé
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SIGNAL eof_pcie_rx1 : STD_LOGIC; -- Indique que la trame est finie (plus de données à envoyer)
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SIGNAL crcok_pcie_rx1 : STD_LOGIC; -- Indique que le CRC et le format est bon (sycnhrone de eof)
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SIGNAL data_pcie_rx2 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem pour RX2
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SIGNAL val_pcie_rx2 : STD_LOGIC;
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SIGNAL sof_pcie_rx2 : STD_LOGIC;
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SIGNAL eof_pcie_rx2 : STD_LOGIC;
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SIGNAL crcok_pcie_rx2: STD_LOGIC;
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SIGNAL data_pcie_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem pour TX
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SIGNAL val_pcie_tx : STD_LOGIC;
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SIGNAL sof_pcie_tx : STD_LOGIC;
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SIGNAL eof_pcie_tx : STD_LOGIC;
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SIGNAL rst_n : std_logic;
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SIGNAL ls485_rx1 : std_logic;
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SIGNAL ls485_tx1 : std_logic;
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SIGNAL ls485_rx2 : std_logic;
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SIGNAL ls485_tx2 : std_logic;
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SIGNAL pmd : std_logic_vector(7 downto 0);
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SIGNAL pmall : std_logic;
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SIGNAL pmalh : std_logic;
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SIGNAL pmrd : std_logic;
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SIGNAL pmwr : std_logic;
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COMPONENT memory_map IS
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GENERIC (
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reg_version : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"10" -- Version du firmware
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);
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PORT (
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clk_sys : IN STD_LOGIC;
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rst_n : IN STD_LOGIC;
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iid : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
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rd_addr : IN STD_LOGIC_VECTOR(NBBIT_ADD_LOCAL-1 DOWNTO 0);
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rd_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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rd_be : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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rd_en : IN STD_LOGIC;
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wr_addr : IN STD_LOGIC_VECTOR(NBBIT_ADD_LOCAL-1 DOWNTO 0);
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wr_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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wr_be : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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wr_en : IN STD_LOGIC;
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wr_busy : OUT STD_LOGIC;
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rst_regn : OUT STD_LOGIC;
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store_enable : OUT STD_LOGIC;
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dma_inprogress : IN STD_LOGIC;
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update_ena : IN STD_LOGIC;
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rx_flushn : OUT STD_LOGIC;
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topcyc : IN STD_LOGIC;
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tx_ena_periodic: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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tx_ena_aper : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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clr_txena_aper : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_base_pa : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_timestamp : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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bufferrx1_full : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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bufferrx2_full : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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buffertx_full : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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newframe_rx1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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newframe_rx2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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newframe_tx : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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rx1_overflow : IN STD_LOGIC;
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rx2_overflow : IN STD_LOGIC;
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tx_overflow : IN STD_LOGIC;
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rx1_badformat : IN STD_LOGIC;
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rx2_badformat : IN STD_LOGIC;
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clk_96 : IN STD_LOGIC;
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rd_force : IN STD_LOGIC;
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data_force : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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empty_force : OUT STD_LOGIC;
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addrr_tx : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
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data_tx : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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rd_datatx : IN STD_LOGIC;
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testpoint : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT manage_dma
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PORT (
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clk_sys : IN STD_LOGIC; -- Clock système à 62.5MHz
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rst_n : IN STD_LOGIC; -- Reset général système
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store_enable : IN STD_LOGIC;
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data_storerx1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Données à stocker.
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val_storerx1 : IN STD_LOGIC; -- Validant du bus data_store(signal write)
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sof_storerx1 : IN STD_LOGIC; -- Indique und début de trame (nouvelle trame). Synchrone du 1er octet envoyé
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eof_storerx1 : IN STD_LOGIC; -- Indique que la trame est finie (plsu de données à envoyer)
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crcok_storerx1 : IN STD_LOGIC; -- Indique que le CRC est bon ou pas (si
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data_storerx2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Données à stocker.
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val_storerx2 : IN STD_LOGIC; -- Validant du bus data_store(signal write)
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sof_storerx2 : IN STD_LOGIC; -- Indique und début de trame (nouvelle trame). Synchrone du 1er octet envoyé
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eof_storerx2 : IN STD_LOGIC; -- Indique que la trame est finie (plsu de données à envoyer)
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crcok_storerx2 : IN STD_LOGIC; -- Indique que le CRC est bon ou pas (si
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data_storetx : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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val_storetx : IN STD_LOGIC;
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sof_storetx : IN STD_LOGIC;
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eof_storetx : IN STD_LOGIC;
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newframe_rx1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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newframe_rx2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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newframe_tx : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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bufferrx1_full : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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bufferrx2_full : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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buffertx_full : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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rx1_overflow : OUT STD_LOGIC;
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rx2_overflow : OUT STD_LOGIC;
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tx_overflow : OUT STD_LOGIC;
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rx1_badformat : OUT STD_LOGIC;
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rx2_badformat : OUT STD_LOGIC;
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dma_inprogress : OUT STD_LOGIC;
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dma_req : OUT STD_LOGIC;
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dma_size : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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dma_ack : IN STD_LOGIC;
|
241 |
|
|
dma_compl : IN STD_LOGIC;
|
242 |
|
|
dma_read : IN STD_LOGIC;
|
243 |
|
|
dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
244 |
|
|
dma_add_dest : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
245 |
|
|
dma_base_pa : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
246 |
|
|
dma_timestamp : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
|
247 |
|
|
);
|
248 |
|
|
END COMPONENT;
|
249 |
|
|
|
250 |
|
|
COMPONENT con_communication_sil
|
251 |
|
|
PORT (
|
252 |
|
|
clk_sys : IN STD_LOGIC;
|
253 |
|
|
rst_n : IN STD_LOGIC;
|
254 |
|
|
baudrate : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
255 |
|
|
actif : IN STD_LOGIC;
|
256 |
|
|
rx1 : IN STD_LOGIC;
|
257 |
|
|
tx1 : OUT STD_LOGIC;
|
258 |
|
|
rx2 : IN STD_LOGIC;
|
259 |
|
|
tx2 : OUT STD_LOGIC;
|
260 |
|
|
copy_ena1 : IN STD_LOGIC;
|
261 |
|
|
copy_ena2 : IN STD_LOGIC;
|
262 |
|
|
layer7_rx1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
263 |
|
|
layer7_soc1 : OUT STD_LOGIC;
|
264 |
|
|
layer7_rd1 : IN STD_LOGIC;
|
265 |
|
|
layer7_newframe1 : OUT STD_LOGIC;
|
266 |
|
|
layer7_comdispo1 : OUT STD_LOGIC;
|
267 |
|
|
layer7_l2ok1 : OUT STD_LOGIC;
|
268 |
|
|
layer7_overflow1 : OUT STD_LOGIC;
|
269 |
|
|
layer7_rx2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
270 |
|
|
layer7_soc2 : OUT STD_LOGIC;
|
271 |
|
|
layer7_rd2 : IN STD_LOGIC;
|
272 |
|
|
layer7_newframe2 : OUT STD_LOGIC;
|
273 |
|
|
layer7_comdispo2 : OUT STD_LOGIC;
|
274 |
|
|
layer7_l2ok2 : OUT STD_LOGIC;
|
275 |
|
|
layer7_overflow2 : OUT STD_LOGIC;
|
276 |
|
|
data_storerx1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
277 |
|
|
val_storerx1 : OUT STD_LOGIC;
|
278 |
|
|
sof_storerx1 : OUT STD_LOGIC;
|
279 |
|
|
eof_storerx1 : OUT STD_LOGIC;
|
280 |
|
|
crcok_storerx1 : OUT STD_LOGIC;
|
281 |
|
|
data_storerx2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
282 |
|
|
val_storerx2 : OUT STD_LOGIC;
|
283 |
|
|
sof_storerx2 : OUT STD_LOGIC;
|
284 |
|
|
eof_storerx2 : OUT STD_LOGIC;
|
285 |
|
|
crcok_storerx2 : OUT STD_LOGIC;
|
286 |
|
|
tx_dat : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
287 |
|
|
val_txdat : IN STD_LOGIC;
|
288 |
|
|
tx_sof : IN STD_LOGIC;
|
289 |
|
|
tx_eof : IN STD_LOGIC;
|
290 |
|
|
txdat_free : OUT STD_LOGIC;
|
291 |
|
|
clr_fifo_tx : IN STD_LOGIC
|
292 |
|
|
);
|
293 |
|
|
END COMPONENT;
|
294 |
|
|
|
295 |
|
|
COMPONENT if_picpmp
|
296 |
|
|
GENERIC (
|
297 |
|
|
version : STD_LOGIC_VECTOR(7 DOWNTO 0));
|
298 |
|
|
PORT (
|
299 |
|
|
clk_sys : IN STD_LOGIC;
|
300 |
|
|
rst_n : IN STD_LOGIC;
|
301 |
|
|
pmd : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
302 |
|
|
pmall : IN STD_LOGIC;
|
303 |
|
|
pmalh : IN STD_LOGIC;
|
304 |
|
|
pmrd : IN STD_LOGIC;
|
305 |
|
|
pmwr : IN STD_LOGIC;
|
306 |
|
|
iid : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
307 |
|
|
tid : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
308 |
|
|
cpy1 : OUT STD_LOGIC;
|
309 |
|
|
cpy2 : OUT STD_LOGIC;
|
310 |
|
|
repli : OUT STD_LOGIC;
|
311 |
|
|
baudrate : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
312 |
|
|
actif : OUT STD_LOGIC;
|
313 |
|
|
topcyc : OUT STD_LOGIC;
|
314 |
|
|
l7_rx1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
315 |
|
|
l7_soc1 : IN STD_LOGIC;
|
316 |
|
|
l7_rd1 : OUT STD_LOGIC;
|
317 |
|
|
l7_comdispo1: IN STD_LOGIC;
|
318 |
|
|
l7_newframe1: IN STD_LOGIC;
|
319 |
|
|
l7_l2ok1 : IN STD_LOGIC;
|
320 |
|
|
l7_overflow1: IN STD_LOGIC;
|
321 |
|
|
l7_rx2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
322 |
|
|
l7_soc2 : IN STD_LOGIC;
|
323 |
|
|
l7_rd2 : OUT STD_LOGIC;
|
324 |
|
|
l7_comdispo2: IN STD_LOGIC;
|
325 |
|
|
l7_newframe2: IN STD_LOGIC;
|
326 |
|
|
l7_l2ok2 : IN STD_LOGIC;
|
327 |
|
|
l7_overflow2: IN STD_LOGIC;
|
328 |
|
|
tx_dat : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
329 |
|
|
val_txdat : OUT STD_LOGIC;
|
330 |
|
|
tx_sof : OUT STD_LOGIC;
|
331 |
|
|
tx_eof : OUT STD_LOGIC;
|
332 |
|
|
txdat_free : IN STD_LOGIC;
|
333 |
|
|
clr_fifo_tx : OUT STD_LOGIC
|
334 |
|
|
);
|
335 |
|
|
END COMPONENT;
|
336 |
|
|
|
337 |
|
|
COMPONENT flux_chgclk
|
338 |
|
|
PORT (
|
339 |
|
|
clks : IN STD_LOGIC;
|
340 |
|
|
clkd : IN STD_LOGIC;
|
341 |
|
|
rst_n : IN STD_LOGIC;
|
342 |
|
|
datas : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
343 |
|
|
vals : IN STD_LOGIC;
|
344 |
|
|
sofs : IN STD_LOGIC;
|
345 |
|
|
eofs : IN STD_LOGIC;
|
346 |
|
|
crcoks : IN STD_LOGIC;
|
347 |
|
|
datad : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
348 |
|
|
vald : OUT STD_LOGIC;
|
349 |
|
|
sofd : OUT STD_LOGIC;
|
350 |
|
|
eofd : OUT STD_LOGIC;
|
351 |
|
|
crcokd : OUT STD_LOGIC
|
352 |
|
|
);
|
353 |
|
|
END COMPONENT;
|
354 |
|
|
|
355 |
|
|
COMPONENT serial_tx
|
356 |
|
|
GENERIC (
|
357 |
|
|
nbbit_div : INTEGER := 10);
|
358 |
|
|
PORT(
|
359 |
|
|
clk_sys : IN STD_LOGIC;
|
360 |
|
|
rst_n : IN STD_LOGIC;
|
361 |
|
|
tc_divclk : IN STD_LOGIC_VECTOR(nbbit_div-1 downto 0);
|
362 |
|
|
start_ser : IN STD_LOGIC;
|
363 |
|
|
tx_dat : IN STD_LOGIC_VECTOR(7 downto 0);
|
364 |
|
|
tx : OUT STD_LOGIC;
|
365 |
|
|
ser_rdy : OUT STD_LOGIC
|
366 |
|
|
);
|
367 |
|
|
END COMPONENT;
|
368 |
|
|
|
369 |
|
|
constant clk_96_period : time := 10416 ps;
|
370 |
|
|
constant pci_period : time := 10 ns;
|
371 |
|
|
|
372 |
|
|
-- Stimulis port 1
|
373 |
|
|
CONSTANT simclk1_period : time := clk_96_period * 1.01;
|
374 |
|
|
SIGNAL simclk1 : STD_LOGIC := '0';
|
375 |
|
|
SIGNAL ser_rdy1 : STD_LOGIC;
|
376 |
|
|
SIGNAL start_ser1 : STD_LOGIC := '0';
|
377 |
|
|
SIGNAL tx_dat1 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
|
378 |
|
|
FILE frames1 : TEXT OPEN READ_MODE IS "frames1.txt";
|
379 |
|
|
|
380 |
|
|
-- Stimulis port 2
|
381 |
|
|
CONSTANT simclk2_period : time := clk_96_period * 0.99;
|
382 |
|
|
SIGNAL simclk2 : STD_LOGIC := '0';
|
383 |
|
|
SIGNAL ser_rdy2 : STD_LOGIC;
|
384 |
|
|
SIGNAL start_ser2 : STD_LOGIC := '0';
|
385 |
|
|
SIGNAL tx_dat2 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
|
386 |
|
|
SIGNAL rx2 : STD_LOGIC := '0';
|
387 |
|
|
FILE frames2 : TEXT OPEN READ_MODE IS "frames2.txt";
|
388 |
|
|
|
389 |
|
|
-- Stimulis port PMP
|
390 |
|
|
CONSTANT pbclk_period : time := 12500 ps;
|
391 |
|
|
signal pbclk : std_logic := '0';
|
392 |
|
|
FILE framespmp : TEXT OPEN READ_MODE IS "frames_pmp.txt";
|
393 |
|
|
|
394 |
|
|
BEGIN
|
395 |
|
|
rstpcie_n <= '0', '1' after 200 ns;
|
396 |
|
|
rst_n <= '0', '1' after 200 ns;
|
397 |
|
|
clk_96 <= NOT(clk_96) after clk_96_period/2;
|
398 |
|
|
clk_pcie <= NOT(clk_pcie) after pci_period/2;
|
399 |
|
|
simclk1 <= NOT(simclk1) AFTER simclk1_period/2;
|
400 |
|
|
simclk2 <= NOT(simclk2) AFTER simclk2_period/2;
|
401 |
|
|
pbclk <= NOT(pbclk) AFTER pbclk_period/2;
|
402 |
|
|
|
403 |
|
|
|
404 |
|
|
PROCESS (clk_96, rst_n)
|
405 |
|
|
BEGIN
|
406 |
|
|
IF (rst_n = '0') THEN
|
407 |
|
|
rst96_n <= '0';
|
408 |
|
|
ELSIF (clk_96'EVENT AND clk_96 = '1') THEN
|
409 |
|
|
rst96_n <= '1';
|
410 |
|
|
END IF;
|
411 |
|
|
END PROCESS;
|
412 |
|
|
|
413 |
|
|
------------------------------
|
414 |
|
|
-- Instantiation du module mémoire
|
415 |
|
|
------------------------------
|
416 |
|
|
inst_mem : memory_map
|
417 |
|
|
GENERIC MAP(
|
418 |
|
|
reg_version => x"25")
|
419 |
|
|
PORT MAP (
|
420 |
|
|
clk_sys => clk_pcie,
|
421 |
|
|
rst_n => rstpcie_n,
|
422 |
|
|
iid => iid,
|
423 |
|
|
rd_addr => rd_addr,
|
424 |
|
|
rd_data => rd_data,
|
425 |
|
|
rd_be => rd_be,
|
426 |
|
|
rd_en => rd_en,
|
427 |
|
|
wr_addr => wr_addr,
|
428 |
|
|
wr_data => wr_data,
|
429 |
|
|
wr_be => wr_be,
|
430 |
|
|
wr_en => wr_en,
|
431 |
|
|
wr_busy => wr_busy,
|
432 |
|
|
rst_regn => rst_regn,
|
433 |
|
|
store_enable => store_enable,
|
434 |
|
|
dma_inprogress => dma_inprogress,
|
435 |
|
|
update_ena => '1',
|
436 |
|
|
rx_flushn => rx_flushn,
|
437 |
|
|
topcyc => topcyc,
|
438 |
|
|
tx_ena_periodic=> tx_ena_periodic,
|
439 |
|
|
tx_ena_aper => tx_ena_aper,
|
440 |
|
|
clr_txena_aper => clr_txena_aper,
|
441 |
|
|
dma_base_pa => dma_base_pa,
|
442 |
|
|
dma_timestamp => dma_timestamp,
|
443 |
|
|
bufferrx1_full => bufferrx1_full,
|
444 |
|
|
bufferrx2_full => bufferrx2_full,
|
445 |
|
|
buffertx_full => buffertx_full,
|
446 |
|
|
newframe_rx1 => newframe_rx1,
|
447 |
|
|
newframe_rx2 => newframe_rx2,
|
448 |
|
|
newframe_tx => newframe_tx,
|
449 |
|
|
rx1_overflow => rx1_overflow,
|
450 |
|
|
rx2_overflow => rx2_overflow,
|
451 |
|
|
tx_overflow => tx_overflow,
|
452 |
|
|
rx1_badformat => rx1_badformat,
|
453 |
|
|
rx2_badformat => rx2_badformat,
|
454 |
|
|
clk_96 => '0',
|
455 |
|
|
rd_force => '0',
|
456 |
|
|
data_force => open,
|
457 |
|
|
empty_force => open,
|
458 |
|
|
addrr_tx => addrr_tx,
|
459 |
|
|
data_tx => data_tx,
|
460 |
|
|
rd_datatx => rd_datatx,
|
461 |
|
|
testpoint => open
|
462 |
|
|
);
|
463 |
|
|
|
464 |
|
|
PROCESS
|
465 |
|
|
BEGIN
|
466 |
|
|
rd_addr <= (OTHERS => '0');
|
467 |
|
|
rd_en <= '0';
|
468 |
|
|
wr_addr <= (OTHERS => '0');
|
469 |
|
|
wr_data <= (OTHERS => '0');
|
470 |
|
|
wr_en <= '0';
|
471 |
|
|
WAIT FOR 1 us;
|
472 |
|
|
WAIT UNTIL clk_pcie'EVENT AND clk_pcie = '1';
|
473 |
|
|
wr_addr <= x"0002";
|
474 |
|
|
wr_data <= x"01000000";
|
475 |
|
|
wr_en <= '1';
|
476 |
|
|
WAIT UNTIL clk_pcie'EVENT AND clk_pcie = '1';
|
477 |
|
|
wr_en <= '0';
|
478 |
|
|
WAIT;
|
479 |
|
|
END PROCESS;
|
480 |
|
|
|
481 |
|
|
|
482 |
|
|
------------------------------
|
483 |
|
|
-- Gestion du DMA
|
484 |
|
|
------------------------------
|
485 |
|
|
inst_dma : manage_dma
|
486 |
|
|
PORT MAP (
|
487 |
|
|
clk_sys => clk_pcie,
|
488 |
|
|
rst_n => rx_flushn,
|
489 |
|
|
store_enable => store_enable,
|
490 |
|
|
data_storerx1 => data_pcie_rx1,
|
491 |
|
|
val_storerx1 => val_pcie_rx1,
|
492 |
|
|
sof_storerx1 => sof_pcie_rx1,
|
493 |
|
|
eof_storerx1 => eof_pcie_rx1,
|
494 |
|
|
crcok_storerx1 => crcok_pcie_rx1,
|
495 |
|
|
data_storerx2 => data_pcie_rx2,
|
496 |
|
|
val_storerx2 => val_pcie_rx2,
|
497 |
|
|
sof_storerx2 => sof_pcie_rx2,
|
498 |
|
|
eof_storerx2 => eof_pcie_rx2,
|
499 |
|
|
crcok_storerx2 => crcok_pcie_rx2,
|
500 |
|
|
data_storetx => data_pcie_tx,
|
501 |
|
|
val_storetx => val_pcie_tx,
|
502 |
|
|
sof_storetx => sof_pcie_tx,
|
503 |
|
|
eof_storetx => eof_pcie_tx,
|
504 |
|
|
newframe_rx1 => newframe_rx1,
|
505 |
|
|
newframe_rx2 => newframe_rx2,
|
506 |
|
|
newframe_tx => newframe_tx,
|
507 |
|
|
bufferrx1_full => bufferrx1_full,
|
508 |
|
|
bufferrx2_full => bufferrx2_full,
|
509 |
|
|
buffertx_full => buffertx_full,
|
510 |
|
|
rx1_overflow => rx1_overflow,
|
511 |
|
|
rx2_overflow => rx2_overflow,
|
512 |
|
|
tx_overflow => tx_overflow,
|
513 |
|
|
rx1_badformat => rx1_badformat,
|
514 |
|
|
rx2_badformat => rx2_badformat,
|
515 |
|
|
dma_inprogress => dma_inprogress,
|
516 |
|
|
dma_req => dma_req,
|
517 |
|
|
dma_size => dma_size,
|
518 |
|
|
dma_ack => dma_ack,
|
519 |
|
|
dma_compl => dma_compl,
|
520 |
|
|
dma_read => dma_read,
|
521 |
|
|
dma_data => dma_data,
|
522 |
|
|
dma_add_dest => dma_add_dest,
|
523 |
|
|
dma_base_pa => x"12345678",
|
524 |
|
|
dma_timestamp => x"12"
|
525 |
|
|
);
|
526 |
|
|
|
527 |
|
|
-----------------------------------------------
|
528 |
|
|
-- Instantiation du module de communication
|
529 |
|
|
-----------------------------------------------
|
530 |
|
|
inst_comm : con_communication_sil
|
531 |
|
|
PORT MAP (
|
532 |
|
|
clk_sys => clk_96,
|
533 |
|
|
rst_n => rst96_n,
|
534 |
|
|
baudrate => baudrate,
|
535 |
|
|
actif => actif,
|
536 |
|
|
rx1 => ls485_rx1,
|
537 |
|
|
tx1 => ls485_tx1,
|
538 |
|
|
rx2 => ls485_rx2,
|
539 |
|
|
tx2 => ls485_tx2,
|
540 |
|
|
copy_ena1 => cpy1,
|
541 |
|
|
copy_ena2 => cpy2,
|
542 |
|
|
layer7_rx1 => l7_rx1,
|
543 |
|
|
layer7_soc1 => l7_soc1,
|
544 |
|
|
layer7_rd1 => l7_rd1,
|
545 |
|
|
layer7_newframe1 => l7_newframe1,
|
546 |
|
|
layer7_comdispo1 => l7_comdispo1,
|
547 |
|
|
layer7_l2ok1 => l7_l2ok1,
|
548 |
|
|
layer7_overflow1 => l7_overflow1,
|
549 |
|
|
layer7_rx2 => l7_rx2,
|
550 |
|
|
layer7_soc2 => l7_soc2,
|
551 |
|
|
layer7_rd2 => l7_rd2,
|
552 |
|
|
layer7_newframe2 => l7_newframe2,
|
553 |
|
|
layer7_comdispo2 => l7_comdispo2,
|
554 |
|
|
layer7_l2ok2 => l7_l2ok2,
|
555 |
|
|
layer7_overflow2 => l7_overflow2,
|
556 |
|
|
data_storerx1 => data_storerx1,
|
557 |
|
|
val_storerx1 => val_storerx1,
|
558 |
|
|
sof_storerx1 => sof_storerx1,
|
559 |
|
|
eof_storerx1 => eof_storerx1,
|
560 |
|
|
crcok_storerx1 => crcok_storerx1,
|
561 |
|
|
data_storerx2 => data_storerx2,
|
562 |
|
|
val_storerx2 => val_storerx2,
|
563 |
|
|
sof_storerx2 => sof_storerx2,
|
564 |
|
|
eof_storerx2 => eof_storerx2,
|
565 |
|
|
crcok_storerx2 => crcok_storerx2,
|
566 |
|
|
tx_dat => tx_dat,
|
567 |
|
|
val_txdat => val_txdat,
|
568 |
|
|
tx_sof => tx_sof,
|
569 |
|
|
tx_eof => tx_eof,
|
570 |
|
|
txdat_free => txdat_free,
|
571 |
|
|
clr_fifo_tx => clr_fifo_tx
|
572 |
|
|
);
|
573 |
|
|
|
574 |
|
|
-----------------------------------------------
|
575 |
|
|
-- Instantiation du module d'interface PIC
|
576 |
|
|
-----------------------------------------------
|
577 |
|
|
inst_pic : if_picpmp
|
578 |
|
|
GENERIC MAP (
|
579 |
|
|
version => x"25")
|
580 |
|
|
PORT MAP (
|
581 |
|
|
clk_sys => clk_96,
|
582 |
|
|
rst_n => rst96_n,
|
583 |
|
|
pmd => pmd,
|
584 |
|
|
pmall => pmall,
|
585 |
|
|
pmalh => pmalh,
|
586 |
|
|
pmrd => pmrd,
|
587 |
|
|
pmwr => pmwr,
|
588 |
|
|
iid => iid,
|
589 |
|
|
tid => tid,
|
590 |
|
|
cpy1 => cpy1,
|
591 |
|
|
cpy2 => cpy2,
|
592 |
|
|
repli => repli,
|
593 |
|
|
baudrate => baudrate,
|
594 |
|
|
actif => actif,
|
595 |
|
|
topcyc => topcyc,
|
596 |
|
|
l7_rx1 => l7_rx1,
|
597 |
|
|
l7_soc1 => l7_soc1,
|
598 |
|
|
l7_rd1 => l7_rd1,
|
599 |
|
|
l7_comdispo1 => l7_comdispo1,
|
600 |
|
|
l7_newframe1 => l7_newframe1,
|
601 |
|
|
l7_l2ok1 => l7_l2ok1,
|
602 |
|
|
l7_overflow1 => l7_overflow1,
|
603 |
|
|
l7_rx2 => l7_rx2,
|
604 |
|
|
l7_soc2 => l7_soc2,
|
605 |
|
|
l7_rd2 => l7_rd2,
|
606 |
|
|
l7_comdispo2 => l7_comdispo2,
|
607 |
|
|
l7_newframe2 => l7_newframe2,
|
608 |
|
|
l7_l2ok2 => l7_l2ok2,
|
609 |
|
|
l7_overflow2 => l7_overflow2,
|
610 |
|
|
tx_dat => tx_dat,
|
611 |
|
|
val_txdat => val_txdat,
|
612 |
|
|
tx_sof => tx_sof,
|
613 |
|
|
tx_eof => tx_eof,
|
614 |
|
|
txdat_free => txdat_free,
|
615 |
|
|
clr_fifo_tx => clr_fifo_tx
|
616 |
|
|
);
|
617 |
|
|
|
618 |
|
|
--------------------------------------------
|
619 |
|
|
-- Changement d'horloge des flux RX1, RX2, TX
|
620 |
|
|
--------------------------------------------
|
621 |
|
|
inst_chgclk_rx1 : flux_chgclk
|
622 |
|
|
PORT MAP(
|
623 |
|
|
clks => clk_96,
|
624 |
|
|
clkd => clk_pcie,
|
625 |
|
|
rst_n => rst96_n,
|
626 |
|
|
datas => data_storerx1,
|
627 |
|
|
vals => val_storerx1,
|
628 |
|
|
sofs => sof_storerx1,
|
629 |
|
|
eofs => eof_storerx1,
|
630 |
|
|
crcoks => crcok_storerx1,
|
631 |
|
|
datad => data_pcie_rx1,
|
632 |
|
|
vald => val_pcie_rx1,
|
633 |
|
|
sofd => sof_pcie_rx1,
|
634 |
|
|
eofd => eof_pcie_rx1,
|
635 |
|
|
crcokd => crcok_pcie_rx1
|
636 |
|
|
);
|
637 |
|
|
|
638 |
|
|
inst_chgclk_rx2 : flux_chgclk
|
639 |
|
|
PORT MAP(
|
640 |
|
|
clks => clk_96,
|
641 |
|
|
clkd => clk_pcie,
|
642 |
|
|
rst_n => rst96_n,
|
643 |
|
|
datas => data_storerx2,
|
644 |
|
|
vals => val_storerx2,
|
645 |
|
|
sofs => sof_storerx2,
|
646 |
|
|
eofs => eof_storerx2,
|
647 |
|
|
crcoks => crcok_storerx2,
|
648 |
|
|
datad => data_pcie_rx2,
|
649 |
|
|
vald => val_pcie_rx2,
|
650 |
|
|
sofd => sof_pcie_rx2,
|
651 |
|
|
eofd => eof_pcie_rx2,
|
652 |
|
|
crcokd => crcok_pcie_rx2
|
653 |
|
|
);
|
654 |
|
|
|
655 |
|
|
tx_val <= txdat_free AND val_txdat; -- On assure que chaque donnée n'est stockée qu'une seule fois
|
656 |
|
|
inst_chgclk_tx : flux_chgclk
|
657 |
|
|
PORT MAP(
|
658 |
|
|
clks => clk_96,
|
659 |
|
|
clkd => clk_pcie,
|
660 |
|
|
rst_n => rst96_n,
|
661 |
|
|
datas => tx_dat,
|
662 |
|
|
vals => tx_val,
|
663 |
|
|
sofs => tx_sof,
|
664 |
|
|
eofs => tx_eof,
|
665 |
|
|
crcoks => '1',
|
666 |
|
|
datad => data_pcie_tx,
|
667 |
|
|
vald => val_pcie_tx,
|
668 |
|
|
sofd => sof_pcie_tx,
|
669 |
|
|
eofd => eof_pcie_tx,
|
670 |
|
|
crcokd => OPEN
|
671 |
|
|
);
|
672 |
|
|
|
673 |
|
|
|
674 |
|
|
-------------------------------------------------
|
675 |
|
|
-- TB
|
676 |
|
|
-------------------------------------------------
|
677 |
|
|
PROCESS
|
678 |
|
|
VARIABLE lread : LINE;
|
679 |
|
|
VARIABLE comments : CHARACTER;
|
680 |
|
|
VARIABLE nb_byte : INTEGER;
|
681 |
|
|
VARIABLE time_frame : TIME;
|
682 |
|
|
VARIABLE value : STD_LOGIC_VECTOR(7 downto 0);
|
683 |
|
|
BEGIN
|
684 |
|
|
start_ser1 <= '0';
|
685 |
|
|
tx_dat1 <= (OTHERS => '0');
|
686 |
|
|
WHILE NOT ENDFILE(frames1) LOOP
|
687 |
|
|
READLINE(frames1, lread);
|
688 |
|
|
READ(lread, comments);
|
689 |
|
|
IF comments/='#' THEN -- the line is not a comment line
|
690 |
|
|
READ(lread, time_frame); -- read the obsolute time to send the frame
|
691 |
|
|
IF (comments = 'A' OR comments = 'a') THEN
|
692 |
|
|
WAIT FOR time_frame - NOW; -- until an absolute time
|
693 |
|
|
ELSE
|
694 |
|
|
WAIT FOR time_frame;
|
695 |
|
|
END IF;
|
696 |
|
|
READ(lread, nb_byte);
|
697 |
|
|
WHILE (nb_byte > 0) LOOP
|
698 |
|
|
IF (ser_rdy1 = '0') THEN
|
699 |
|
|
WAIT UNTIL ser_rdy1 = '1';
|
700 |
|
|
END IF;
|
701 |
|
|
WAIT UNTIL simclk1'EVENT and simclk1 = '0';
|
702 |
|
|
HREAD(lread, value);
|
703 |
|
|
tx_dat1 <= value;
|
704 |
|
|
start_ser1 <= '1';
|
705 |
|
|
WAIT UNTIL simclk1'EVENT and simclk1 = '0';
|
706 |
|
|
start_ser1 <= '0';
|
707 |
|
|
nb_byte := nb_byte - 1 ;
|
708 |
|
|
END LOOP;
|
709 |
|
|
END IF;
|
710 |
|
|
END LOOP;
|
711 |
|
|
WAIT;
|
712 |
|
|
END PROCESS;
|
713 |
|
|
|
714 |
|
|
inst_serial_tx1: serial_tx
|
715 |
|
|
GENERIC MAP (
|
716 |
|
|
nbbit_div => 11)
|
717 |
|
|
PORT MAP(
|
718 |
|
|
clk_sys => simclk1,
|
719 |
|
|
rst_n => rst_n,
|
720 |
|
|
tc_divclk => CONV_STD_LOGIC_VECTOR(7,11),
|
721 |
|
|
tx => ls485_rx1,
|
722 |
|
|
ser_rdy => ser_rdy1,
|
723 |
|
|
start_ser => start_ser1,
|
724 |
|
|
tx_dat => tx_dat1
|
725 |
|
|
);
|
726 |
|
|
|
727 |
|
|
PROCESS
|
728 |
|
|
VARIABLE lread : LINE;
|
729 |
|
|
VARIABLE comments : CHARACTER;
|
730 |
|
|
VARIABLE nb_byte : INTEGER;
|
731 |
|
|
VARIABLE time_frame : TIME;
|
732 |
|
|
VARIABLE value : STD_LOGIC_VECTOR(7 downto 0);
|
733 |
|
|
BEGIN
|
734 |
|
|
start_ser2 <= '0';
|
735 |
|
|
tx_dat2 <= (OTHERS => '0');
|
736 |
|
|
WHILE NOT ENDFILE(frames2) LOOP
|
737 |
|
|
READLINE(frames2, lread);
|
738 |
|
|
READ(lread, comments);
|
739 |
|
|
IF comments/='#' THEN -- the line is not a comment line
|
740 |
|
|
READ(lread, time_frame); -- read the obsolute time to send the frame
|
741 |
|
|
IF (comments = 'A' OR comments = 'a') THEN
|
742 |
|
|
WAIT FOR time_frame - NOW; -- until an absolute time
|
743 |
|
|
ELSE
|
744 |
|
|
WAIT FOR time_frame;
|
745 |
|
|
END IF;
|
746 |
|
|
READ(lread, nb_byte);
|
747 |
|
|
WHILE (nb_byte > 0) LOOP
|
748 |
|
|
IF (ser_rdy2 = '0') THEN
|
749 |
|
|
WAIT UNTIL ser_rdy2 = '1';
|
750 |
|
|
END IF;
|
751 |
|
|
WAIT UNTIL simclk2'EVENT and simclk2 = '0';
|
752 |
|
|
HREAD(lread, value);
|
753 |
|
|
tx_dat2 <= value;
|
754 |
|
|
start_ser2 <= '1';
|
755 |
|
|
WAIT UNTIL simclk2'EVENT and simclk2 = '0';
|
756 |
|
|
start_ser2 <= '0';
|
757 |
|
|
nb_byte := nb_byte - 1 ;
|
758 |
|
|
END LOOP;
|
759 |
|
|
END IF;
|
760 |
|
|
END LOOP;
|
761 |
|
|
WAIT;
|
762 |
|
|
END PROCESS;
|
763 |
|
|
|
764 |
|
|
inst_serial_tx2: serial_tx
|
765 |
|
|
GENERIC MAP (
|
766 |
|
|
nbbit_div => 11)
|
767 |
|
|
PORT MAP(
|
768 |
|
|
clk_sys => simclk2,
|
769 |
|
|
rst_n => rst_n,
|
770 |
|
|
tc_divclk => CONV_STD_LOGIC_VECTOR(7,11),
|
771 |
|
|
tx => ls485_rx2,
|
772 |
|
|
ser_rdy => ser_rdy2,
|
773 |
|
|
start_ser => start_ser2,
|
774 |
|
|
tx_dat => tx_dat2
|
775 |
|
|
);
|
776 |
|
|
|
777 |
|
|
PROCESS
|
778 |
|
|
VARIABLE lread : LINE;
|
779 |
|
|
VARIABLE comments : CHARACTER;
|
780 |
|
|
VARIABLE nb_byte : INTEGER;
|
781 |
|
|
VARIABLE time_frame : TIME;
|
782 |
|
|
VARIABLE value : STD_LOGIC_VECTOR(7 downto 0);
|
783 |
|
|
VARIABLE com : STD_LOGIC_VECTOR(7 downto 0);
|
784 |
|
|
VARIABLE add : STD_LOGIC_VECTOR(7 downto 0);
|
785 |
|
|
BEGIN
|
786 |
|
|
pmd <= (OTHERS => 'Z');
|
787 |
|
|
pmall <= '0';
|
788 |
|
|
pmalh <= '0';
|
789 |
|
|
pmrd <= '0';
|
790 |
|
|
pmwr <= '0';
|
791 |
|
|
WHILE NOT ENDFILE(framespmp) LOOP
|
792 |
|
|
READLINE(framespmp, lread);
|
793 |
|
|
READ(lread, comments);
|
794 |
|
|
IF comments/='#' THEN -- the line is not a comment line
|
795 |
|
|
READ(lread, time_frame); -- read the obsolute time to send the frame
|
796 |
|
|
IF (comments = 'A' OR comments = 'a') THEN
|
797 |
|
|
WAIT FOR time_frame - NOW; -- until an absolute time
|
798 |
|
|
ELSE
|
799 |
|
|
WAIT FOR time_frame;
|
800 |
|
|
END IF;
|
801 |
|
|
READ(lread, nb_byte);
|
802 |
|
|
HREAD(lread, value);
|
803 |
|
|
com := value;
|
804 |
|
|
add := '0' & com(7 DOWNTO 1);
|
805 |
|
|
nb_byte := nb_byte - 1;
|
806 |
|
|
WAIT UNTIL pbclk'EVENT and pbclk = '1';
|
807 |
|
|
WHILE (nb_byte > 0) LOOP
|
808 |
|
|
HREAD(lread, value);
|
809 |
|
|
pmd <= add;
|
810 |
|
|
WAIT UNTIL pbclk'EVENT and pbclk = '1';
|
811 |
|
|
pmall <= '1';
|
812 |
|
|
WAIT UNTIL pbclk'EVENT and pbclk = '1';
|
813 |
|
|
pmall <= '0';
|
814 |
|
|
WAIT UNTIL pbclk'EVENT and pbclk = '1';
|
815 |
|
|
pmd <= x"00";
|
816 |
|
|
WAIT UNTIL pbclk'EVENT and pbclk = '1';
|
817 |
|
|
pmalh <= '1';
|
818 |
|
|
WAIT UNTIL pbclk'EVENT and pbclk = '1';
|
819 |
|
|
pmalh <= '0';
|
820 |
|
|
WAIT UNTIL pbclk'EVENT and pbclk = '1';
|
821 |
|
|
IF (com(0) = '1') THEN
|
822 |
|
|
pmd <= (OTHERS => 'Z');
|
823 |
|
|
WAIT UNTIL pbclk'EVENT and pbclk = '1';
|
824 |
|
|
pmrd <= '1';
|
825 |
|
|
WAIT UNTIL pbclk'EVENT and pbclk = '1';
|
826 |
|
|
pmrd <= '0';
|
827 |
|
|
ELSE
|
828 |
|
|
pmd <= value;
|
829 |
|
|
pmwr <= '1';
|
830 |
|
|
WAIT UNTIL pbclk'EVENT and pbclk = '1';
|
831 |
|
|
pmwr <= '0';
|
832 |
|
|
WAIT UNTIL pbclk'EVENT and pbclk = '1';
|
833 |
|
|
WAIT UNTIL pbclk'EVENT and pbclk = '1';
|
834 |
|
|
pmd <= (OTHERS => 'Z');
|
835 |
|
|
END IF;
|
836 |
|
|
nb_byte := nb_byte - 1;
|
837 |
|
|
IF (add /= x"0E" AND add /= x"0F" AND add /= x"10") THEN
|
838 |
|
|
add := add + 1;
|
839 |
|
|
END IF;
|
840 |
|
|
END LOOP;
|
841 |
|
|
END IF;
|
842 |
|
|
END LOOP;
|
843 |
|
|
WAIT;
|
844 |
|
|
END PROCESS;
|
845 |
|
|
|
846 |
|
|
END rtl;
|
847 |
|
|
|