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DavidRAMBA |
#=============================================================================
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# TITRE : TOP_FPGACOSIL2
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# DESCRIPTION :
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# Fichier de contrainte du FPGA Concentrateur SIL2
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# FICHIER : top_fpgacosil2.ucf
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#=============================================================================
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# CREATION
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# DATE AUTEUR PROJET REVISION
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# 10/04/2014 DRA SATURN V1.0
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#=============================================================================
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# HISTORIQUE DES MODIFICATIONS :
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# DATE AUTEUR PROJET REVISION
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#=============================================================================
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#-----------------------------
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# definition des timings
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#-----------------------------
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NET "clk_24" TNM_NET = "clk_24";
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TIMESPEC TS_clk_24 = PERIOD "clk_24" 35 ns HIGH 50 %;
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NET "inst_pcieif/s6_pcie_v1_4_i/gt_refclk_out[0]" TNM_NET = "inst_pcieif/s6_pcie_v1_4_i/gt_refclk_out<0>";
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TIMESPEC TS_inst_pcieif_s6_pcie_v1_4_i_gt_refclk_out_0_ = PERIOD "inst_pcieif/s6_pcie_v1_4_i/gt_refclk_out<0>" 10 ns HIGH 50 %;
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TIMEGRP "pmp_dat_uc1" OFFSET = IN 12.5 ns VALID 36 ns BEFORE "pmwr_uc1" FALLING;
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INST "pmd_uc1[0]" TNM = "pmp_dat_uc1";
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INST "pmd_uc1[1]" TNM = "pmp_dat_uc1";
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INST "pmd_uc1[2]" TNM = "pmp_dat_uc1";
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INST "pmd_uc1[3]" TNM = "pmp_dat_uc1";
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INST "pmd_uc1[4]" TNM = "pmp_dat_uc1";
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INST "pmd_uc1[5]" TNM = "pmp_dat_uc1";
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INST "pmd_uc1[6]" TNM = "pmp_dat_uc1";
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INST "pmd_uc1[7]" TNM = "pmp_dat_uc1";
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TIMEGRP "pmp_add_uc1" OFFSET = IN 12.5 ns VALID 36 ns BEFORE "pmall_uc1" RISING;
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INST "pmd_uc1[0]" TNM = "pmp_add_uc1";
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INST "pmd_uc1[1]" TNM = "pmp_add_uc1";
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INST "pmd_uc1[2]" TNM = "pmp_add_uc1";
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INST "pmd_uc1[3]" TNM = "pmp_add_uc1";
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INST "pmd_uc1[4]" TNM = "pmp_add_uc1";
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INST "pmd_uc1[5]" TNM = "pmp_add_uc1";
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INST "pmd_uc1[6]" TNM = "pmp_add_uc1";
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TIMEGRP "pmp_dat_uc2" OFFSET = IN 12.5 ns VALID 36 ns BEFORE "pmwr_uc2" FALLING;
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INST "pmd_uc2[0]" TNM = "pmp_dat_uc2";
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INST "pmd_uc2[1]" TNM = "pmp_dat_uc2";
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INST "pmd_uc2[2]" TNM = "pmp_dat_uc2";
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INST "pmd_uc2[3]" TNM = "pmp_dat_uc2";
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INST "pmd_uc2[4]" TNM = "pmp_dat_uc2";
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INST "pmd_uc2[5]" TNM = "pmp_dat_uc2";
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INST "pmd_uc2[6]" TNM = "pmp_dat_uc2";
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INST "pmd_uc2[7]" TNM = "pmp_dat_uc2";
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TIMEGRP "pmp_add_uc2" OFFSET = IN 12.5 ns VALID 36 ns BEFORE "pmall_uc2" RISING;
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INST "pmd_uc2[0]" TNM = "pmp_add_uc2";
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INST "pmd_uc2[1]" TNM = "pmp_add_uc2";
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INST "pmd_uc2[2]" TNM = "pmp_add_uc2";
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INST "pmd_uc2[3]" TNM = "pmp_add_uc2";
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INST "pmd_uc2[4]" TNM = "pmp_add_uc2";
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INST "pmd_uc2[5]" TNM = "pmp_add_uc2";
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INST "pmd_uc2[6]" TNM = "pmp_add_uc2";
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#-----------------------------
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# Valeurs d'inititalisation
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#-----------------------------
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# Commande des MOSFET des alims isolées. Forçage à '0' à la config car pas de reset sur ce process
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INST "cde_high" INIT = 1'b0;
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INST "cde_low" INIT = 1'b0;
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#-----------------------------
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# Definition du pinning
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#-----------------------------
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INST "inst_pcieif/s6_pcie_v1_4_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i" LOC = GTPA1_DUAL_X0Y0;
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NET "cclk" LOC = R15;
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NET "cdehigh_5vid" LOC = D17;
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NET "cdehigh_5vls1" LOC = C17;
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NET "cdehigh_5vls2" LOC = F14;
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NET "cdehigh_5vlsm2" LOC = H12;
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NET "cdehigh_5vcan" LOC = E16;
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NET "cdelow_5vid" LOC = G14;
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NET "cdelow_5vls1" LOC = F16;
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NET "cdelow_5vls2" LOC = C18;
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NET "cdelow_5vlsm2" LOC = D18;
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NET "cdelow_5vcan" LOC = G13;
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NET "clk_24" LOC = G11;
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NET "cso_b" LOC = V3;
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NET "din_miso" LOC = R13;
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NET "interrupt" LOC = V13;
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NET "led_confok" LOC = P12;
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NET "led_fail" LOC = U13;
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NET "led_run" LOC = P15;
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NET "ls485_de1" LOC = E18;
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NET "ls485_de2" LOC = F18;
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NET "ls485_ren1" LOC = K12;
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NET "ls485_ren2" LOC = H13;
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NET "ls485_rx1" LOC = K13;
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NET "ls485_rx2" LOC = H14;
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NET "ls485_tx1" LOC = F17;
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NET "ls485_tx2" LOC = H15;
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NET "mosi" LOC = T13;
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NET "pci_clk_p" LOC = B8;
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NET "pci_clk_n" LOC = A8;
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NET "pci_exp_rxn" LOC = C5;
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NET "pci_exp_rxp" LOC = D5;
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NET "pci_exp_txn" LOC = A4;
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NET "pci_exp_txp" LOC = B4;
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NET "pci_rstn" LOC = J13;
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NET "pci_spare" LOC = K15;
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NET "pci_waken" LOC = K14;
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NET "pic_rx" LOC = P18;
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NET "pic_sck" LOC = L15;
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NET "pic_sdi" LOC = H17;
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NET "pic_sdo" LOC = L16;
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NET "pic_spare_uc1[0]" LOC = L18;
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NET "pic_spare_uc1[1]" LOC = M16;
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NET "pic_spare_uc1[2]" LOC = M18;
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NET "pic_spare_uc1[3]" LOC = N17;
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NET "pic_spare_uc2[2]" LOC = R3;
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NET "pic_spare_uc2[3]" LOC = V5;
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NET "pic_spare_uc2[4]" LOC = U5;
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NET "pic_ssn" LOC = H18;
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NET "pic_tx" LOC = P17;
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NET "pmalh_uc1" LOC = V9;
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NET "pmall_uc1" LOC = T9;
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NET "pmd_uc1[0]" LOC = P8;
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NET "pmd_uc1[1]" LOC = N7;
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NET "pmd_uc1[2]" LOC = V7;
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NET "pmd_uc1[3]" LOC = U7;
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NET "pmd_uc1[4]" LOC = V8;
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NET "pmd_uc1[5]" LOC = U8;
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NET "pmd_uc1[6]" LOC = N8;
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NET "pmd_uc1[7]" LOC = M8;
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NET "pmrd_uc1" LOC = T6;
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NET "pmwr_uc1" LOC = T8;
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NET "pmalh_uc2" LOC = J1;
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NET "pmall_uc2" LOC = K4;
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NET "pmd_uc2[0]" LOC = L3;
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NET "pmd_uc2[1]" LOC = L4;
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NET "pmd_uc2[2]" LOC = K1;
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NET "pmd_uc2[3]" LOC = K2;
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NET "pmd_uc2[4]" LOC = L1;
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NET "pmd_uc2[5]" LOC = L2;
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NET "pmd_uc2[6]" LOC = M1;
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NET "pmd_uc2[7]" LOC = M3;
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NET "pmrd_uc2" LOC = J3;
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NET "pmwr_uc2" LOC = H2;
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NET "power_rstn" LOC = T18;
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NET "prog_b" LOC = N5;
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NET "rstfpga_uc1n" LOC = J18;
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NET "rstfpga_uc2n" LOC = T3;
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NET "rst_n" LOC = K18;
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NET "tp[21]" LOC = B3;
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NET "tp[23]" LOC = E6;
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NET "tp[22]" LOC = A3;
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NET "tp[24]" LOC = F7;
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NET "tp[25]" LOC = G8;
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NET "tp[27]" LOC = G9;
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NET "tp[26]" LOC = E8;
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NET "uc_pmacs1" LOC = E3;
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NET "uc_pmacs2" LOC = H5;
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NET "uc_pmalh" LOC = H4;
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NET "uc_pmall" LOC = K5;
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NET "uc_pmd[0]" LOC = F2;
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NET "uc_pmd[1]" LOC = J6;
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NET "uc_pmd[2]" LOC = J7;
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NET "uc_pmd[3]" LOC = G1;
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NET "uc_pmd[4]" LOC = G3;
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NET "uc_pmd[5]" LOC = K6;
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NET "uc_pmd[6]" LOC = L7;
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NET "uc_pmd[7]" LOC = H3;
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NET "uc_pmrd" LOC = F1;
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NET "uc_pmwr" LOC = L5;
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NET "uc_sck" LOC = F4;
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NET "uc_sdi" LOC = D1;
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NET "uc_sdo" LOC = D2;
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NET "uc_ssn" LOC = F3;
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NET "wp_flashn" LOC = H1;
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NET "cmd_fpga_pmp2" LOC = N16;
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NET "rst_switchn" LOC = U18;
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NET "ext_pull" LOC = T15;
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#-----------------------------
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# Definition des niveaux électriques
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#-----------------------------
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NET "cclk" IOSTANDARD = LVCMOS33;
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NET "cdehigh_5vid" IOSTANDARD = LVCMOS33;
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NET "cdehigh_5vls1" IOSTANDARD = LVCMOS33;
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NET "cdehigh_5vls2" IOSTANDARD = LVCMOS33;
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NET "cdehigh_5vlsm2" IOSTANDARD = LVCMOS33;
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NET "cdehigh_5vcan" IOSTANDARD = LVCMOS33;
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NET "cdelow_5vid" IOSTANDARD = LVCMOS33;
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NET "cdelow_5vls1" IOSTANDARD = LVCMOS33;
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NET "cdelow_5vls2" IOSTANDARD = LVCMOS33;
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NET "cdelow_5vlsm2" IOSTANDARD = LVCMOS33;
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NET "cdelow_5vcan" IOSTANDARD = LVCMOS33;
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NET "clk_24" IOSTANDARD = LVCMOS33;
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NET "cso_b" IOSTANDARD = LVCMOS33;
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NET "din_miso" IOSTANDARD = LVCMOS33;
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NET "interrupt" IOSTANDARD = LVCMOS33;
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NET "led_confok" IOSTANDARD = LVCMOS33;
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NET "led_fail" IOSTANDARD = LVCMOS33;
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NET "led_run" IOSTANDARD = LVCMOS33;
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NET "ls485_de1" IOSTANDARD = LVCMOS33;
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NET "ls485_de2" IOSTANDARD = LVCMOS33;
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NET "ls485_ren1" IOSTANDARD = LVCMOS33;
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NET "ls485_ren2" IOSTANDARD = LVCMOS33;
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NET "ls485_rx1" IOSTANDARD = LVCMOS33;
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NET "ls485_rx2" IOSTANDARD = LVCMOS33;
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NET "ls485_tx1" IOSTANDARD = LVCMOS33;
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NET "ls485_tx2" IOSTANDARD = LVCMOS33;
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NET "mosi" IOSTANDARD = LVCMOS33;
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NET "pci_clk_p" IOSTANDARD = LVCMOS33;
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NET "pci_exp_rxp" IOSTANDARD = LVCMOS33;
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NET "pci_exp_txp" IOSTANDARD = LVCMOS33;
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NET "pci_rstn" IOSTANDARD = LVCMOS33;
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NET "pci_spare" IOSTANDARD = LVCMOS33;
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NET "pci_waken" IOSTANDARD = LVCMOS33;
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NET "pic_rx" IOSTANDARD = LVCMOS33;
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NET "pic_sck" IOSTANDARD = LVCMOS33;
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NET "pic_sdi" IOSTANDARD = LVCMOS33;
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NET "pic_sdo" IOSTANDARD = LVCMOS33;
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NET "pic_spare_uc1[0]" IOSTANDARD = LVCMOS33;
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NET "pic_spare_uc1[1]" IOSTANDARD = LVCMOS33;
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NET "pic_spare_uc1[2]" IOSTANDARD = LVCMOS33;
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NET "pic_spare_uc1[3]" IOSTANDARD = LVCMOS33;
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NET "pic_spare_uc2[2]" IOSTANDARD = LVCMOS33;
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NET "pic_spare_uc2[3]" IOSTANDARD = LVCMOS33;
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NET "pic_spare_uc2[4]" IOSTANDARD = LVCMOS33;
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NET "pic_ssn" IOSTANDARD = LVCMOS33;
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NET "pic_tx" IOSTANDARD = LVCMOS33;
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NET "pmalh_uc1" IOSTANDARD = LVCMOS33;
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NET "pmall_uc1" IOSTANDARD = LVCMOS33;
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NET "pmd_uc1[0]" IOSTANDARD = LVCMOS33;
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NET "pmd_uc1[1]" IOSTANDARD = LVCMOS33;
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NET "pmd_uc1[2]" IOSTANDARD = LVCMOS33;
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NET "pmd_uc1[3]" IOSTANDARD = LVCMOS33;
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| 234 |
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NET "pmd_uc1[4]" IOSTANDARD = LVCMOS33;
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| 235 |
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NET "pmd_uc1[5]" IOSTANDARD = LVCMOS33;
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NET "pmd_uc1[6]" IOSTANDARD = LVCMOS33;
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NET "pmd_uc1[7]" IOSTANDARD = LVCMOS33;
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NET "pmrd_uc1" IOSTANDARD = LVCMOS33;
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NET "pmwr_uc1" IOSTANDARD = LVCMOS33;
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NET "pmalh_uc2" IOSTANDARD = LVCMOS33;
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NET "pmall_uc2" IOSTANDARD = LVCMOS33;
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NET "pmd_uc2[0]" IOSTANDARD = LVCMOS33;
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| 243 |
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NET "pmd_uc2[1]" IOSTANDARD = LVCMOS33;
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| 244 |
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NET "pmd_uc2[2]" IOSTANDARD = LVCMOS33;
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| 245 |
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NET "pmd_uc2[3]" IOSTANDARD = LVCMOS33;
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| 246 |
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NET "pmd_uc2[4]" IOSTANDARD = LVCMOS33;
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| 247 |
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NET "pmd_uc2[5]" IOSTANDARD = LVCMOS33;
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| 248 |
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NET "pmd_uc2[6]" IOSTANDARD = LVCMOS33;
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| 249 |
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NET "pmd_uc2[7]" IOSTANDARD = LVCMOS33;
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| 250 |
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NET "pmrd_uc2" IOSTANDARD = LVCMOS33;
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| 251 |
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NET "pmwr_uc2" IOSTANDARD = LVCMOS33;
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| 252 |
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NET "power_rstn" IOSTANDARD = LVCMOS33;
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| 253 |
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NET "prog_b" IOSTANDARD = LVCMOS33;
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| 254 |
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NET "rstfpga_uc1n" IOSTANDARD = LVCMOS33;
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| 255 |
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NET "rstfpga_uc2n" IOSTANDARD = LVCMOS33;
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NET "rst_n" IOSTANDARD = LVCMOS33;
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| 257 |
|
|
NET "tp[21]" IOSTANDARD = LVCMOS33;
|
| 258 |
|
|
NET "tp[22]" IOSTANDARD = LVCMOS33;
|
| 259 |
|
|
NET "tp[23]" IOSTANDARD = LVCMOS33;
|
| 260 |
|
|
NET "tp[24]" IOSTANDARD = LVCMOS33;
|
| 261 |
|
|
NET "tp[25]" IOSTANDARD = LVCMOS33;
|
| 262 |
|
|
NET "tp[26]" IOSTANDARD = LVCMOS33;
|
| 263 |
|
|
NET "tp[27]" IOSTANDARD = LVCMOS33;
|
| 264 |
|
|
NET "uc_pmacs1" IOSTANDARD = LVCMOS33;
|
| 265 |
|
|
NET "uc_pmacs2" IOSTANDARD = LVCMOS33;
|
| 266 |
|
|
NET "uc_pmalh" IOSTANDARD = LVCMOS33;
|
| 267 |
|
|
NET "uc_pmall" IOSTANDARD = LVCMOS33;
|
| 268 |
|
|
NET "uc_pmd[0]" IOSTANDARD = LVCMOS33;
|
| 269 |
|
|
NET "uc_pmd[1]" IOSTANDARD = LVCMOS33;
|
| 270 |
|
|
NET "uc_pmd[2]" IOSTANDARD = LVCMOS33;
|
| 271 |
|
|
NET "uc_pmd[3]" IOSTANDARD = LVCMOS33;
|
| 272 |
|
|
NET "uc_pmd[4]" IOSTANDARD = LVCMOS33;
|
| 273 |
|
|
NET "uc_pmd[5]" IOSTANDARD = LVCMOS33;
|
| 274 |
|
|
NET "uc_pmd[6]" IOSTANDARD = LVCMOS33;
|
| 275 |
|
|
NET "uc_pmd[7]" IOSTANDARD = LVCMOS33;
|
| 276 |
|
|
NET "uc_pmrd" IOSTANDARD = LVCMOS33;
|
| 277 |
|
|
NET "uc_pmwr" IOSTANDARD = LVCMOS33;
|
| 278 |
|
|
NET "uc_sck" IOSTANDARD = LVCMOS33;
|
| 279 |
|
|
NET "uc_sdi" IOSTANDARD = LVCMOS33;
|
| 280 |
|
|
NET "uc_sdo" IOSTANDARD = LVCMOS33;
|
| 281 |
|
|
NET "uc_ssn" IOSTANDARD = LVCMOS33;
|
| 282 |
|
|
NET "wp_flashn" IOSTANDARD = LVCMOS33;
|
| 283 |
|
|
NET "cmd_fpga_pmp2" IOSTANDARD = LVCMOS33;
|
| 284 |
|
|
NET "rst_switchn" IOSTANDARD = LVCMOS33;
|
| 285 |
|
|
NET "ext_pull" IOSTANDARD = LVCMOS33;
|
| 286 |
|
|
|
| 287 |
|
|
# Definition slew rate pour améliorer les performances de l'interface PMP
|
| 288 |
|
|
NET "pmd_uc1[0]" SLEW = FAST;
|
| 289 |
|
|
NET "pmd_uc1[1]" SLEW = FAST;
|
| 290 |
|
|
NET "pmd_uc1[2]" SLEW = FAST;
|
| 291 |
|
|
NET "pmd_uc1[3]" SLEW = FAST;
|
| 292 |
|
|
NET "pmd_uc1[4]" SLEW = FAST;
|
| 293 |
|
|
NET "pmd_uc1[5]" SLEW = FAST;
|
| 294 |
|
|
NET "pmd_uc1[6]" SLEW = FAST;
|
| 295 |
|
|
NET "pmd_uc1[7]" SLEW = FAST;
|
| 296 |
|
|
NET "pmd_uc2[0]" SLEW = FAST;
|
| 297 |
|
|
NET "pmd_uc2[1]" SLEW = FAST;
|
| 298 |
|
|
NET "pmd_uc2[2]" SLEW = FAST;
|
| 299 |
|
|
NET "pmd_uc2[3]" SLEW = FAST;
|
| 300 |
|
|
NET "pmd_uc2[4]" SLEW = FAST;
|
| 301 |
|
|
NET "pmd_uc2[5]" SLEW = FAST;
|
| 302 |
|
|
NET "pmd_uc2[6]" SLEW = FAST;
|
| 303 |
|
|
NET "pmd_uc2[7]" SLEW = FAST;
|
| 304 |
|
|
NET "cmd_fpga_pmp2" SLEW = FAST;
|
