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[/] [saturn/] [trunk/] [FPGA MIOSIL2/] [fpga_miosil2/] [top_miosil2.ucf] - Blame information for rev 2

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1 2 DavidRAMBA 
#=============================================================================
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#  TITRE : TOP_MIOSIL2
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#  DESCRIPTION :
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#        Fichier de contrainte du FPGA top_miosil2
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#  FICHIER :        top_miosil2.ucf
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#=============================================================================
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#  CREATION
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#  DATE       AUTEUR    PROJET  REVISION
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#  10/04/2014   DRA        SATURN       V1.0
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#=============================================================================
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#  HISTORIQUE  DES  MODIFICATIONS :
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#  DATE       AUTEUR    PROJET  REVISION
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#=============================================================================
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#-----------------------------
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# definition des timings
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#-----------------------------
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#Clock à 24MHZ
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NET "clk_24" TNM_NET = "clk_24";
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TIMESPEC TS_clk_24 = PERIOD "clk_24" 35 ns HIGH 50 %;
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#clock sclk à 25MHz
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NET "pic_sclk" TNM_NET = "pic_sclk";
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TIMESPEC TS_pic_sclk = PERIOD "pic_sclk" 35 ns HIGH 50 %;
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# Cross clocking entre sclk et clk_96
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NET "clk_96" TNM_NET = "clk_96";
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TIMESPEC TS_cross_domain = FROM "pic_sclk" TO "clk_96" 12 ns;
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# Setup et Hold pour l'interface SPI
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TIMEGRP "spi_grp" OFFSET = IN 15 ns VALID 15 ns BEFORE "pic_sclk" RISING;
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INST "pic_sdo" TNM = "spi_grp";
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NET "pic_sdi" OFFSET = OUT 10 ns AFTER "pic_sclk" FALLING;
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#-----------------------------
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# Valeurs d'inititalisation
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#-----------------------------
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# Commande des MOSFET des alims isolées. Forçage à '0' à la config car pas de reset sur ce process
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INST "cde_high" INIT = 1'b0;
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INST "cde_low" INIT = 1'b0;
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#-----------------------------
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# Definition du pinning
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#-----------------------------
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NET "cclk" LOC = P70;
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NET "cde_diag1" LOC = P102;
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NET "cde_diag2" LOC = P101;
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NET "cdehigh_5vid" LOC = P105;
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NET "cdehigh_5vls1" LOC = P100;
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NET "cdehigh_5vls2" LOC = P98;
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NET "cdelow_5vid" LOC = P104;
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NET "cdelow_5vls1" LOC = P99;
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NET "cdelow_5vls2" LOC = P97;
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NET "clk_24" LOC = P88;
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NET "cso_b" LOC = P38;
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NET "din_miso" LOC = P65;
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NET "led_confok" LOC = P79;
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NET "led_fail" LOC = P75;
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NET "led_run" LOC = P78;
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NET "ls485_de1" LOC = P142;
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NET "ls485_de2" LOC = P134;
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NET "ls485_ren1" LOC = P141;
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NET "ls485_ren2" LOC = P133;
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NET "ls485_rx1" LOC = P140;
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NET "ls485_rx2" LOC = P132;
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NET "ls485_tx1" LOC = P139;
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NET "ls485_tx2" LOC = P131;
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NET "mosi" LOC = P64;
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NET "pic_rx" LOC = P33;
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NET "pic_sclk" LOC = P14;
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NET "pic_sdi" LOC = P10;
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NET "pic_sdo" LOC = P12;
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NET "pic_spare[0]" LOC = P29;
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NET "pic_spare[1]" LOC = P27;
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NET "pic_spare[2]" LOC = P26;
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NET "pic_spare[3]" LOC = P24;
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NET "pic_ssn" LOC = P11;
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NET "pic_tx" LOC = P34;
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NET "power_rstn" LOC = P50;
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NET "prog_b" LOC = P40;
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NET "rst_fpgan" LOC = P84;
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NET "rst_n" LOC = P85;
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NET "spare[0]" LOC = P119;
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NET "spare[1]" LOC = P118;
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NET "spare[2]" LOC = P117;
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NET "spare[3]" LOC = P116;
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NET "spare[4]" LOC = P115;
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NET "spare[5]" LOC = P114;
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NET "spare[6]" LOC = P112;
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NET "spare[7]" LOC = P111;
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NET "tp7" LOC = P126;
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NET "tp8" LOC = P123;
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NET "tp9" LOC = P82;
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NET "wp_flashn" LOC = P80;
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NET "pic_refclki" LOC = P2;
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#-----------------------------
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# Definition des niveaux électriques
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#-----------------------------
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NET "cclk" IOSTANDARD = LVCMOS33;
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NET "cde_diag1" IOSTANDARD = LVCMOS33;
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NET "cde_diag2" IOSTANDARD = LVCMOS33;
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NET "cdehigh_5vid" IOSTANDARD = LVCMOS33;
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NET "cdehigh_5vls1" IOSTANDARD = LVCMOS33;
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NET "cdehigh_5vls2" IOSTANDARD = LVCMOS33;
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NET "cdelow_5vid" IOSTANDARD = LVCMOS33;
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NET "cdelow_5vls1" IOSTANDARD = LVCMOS33;
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NET "cdelow_5vls2" IOSTANDARD = LVCMOS33;
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NET "clk_24" IOSTANDARD = LVCMOS33;
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NET "cso_b" IOSTANDARD = LVCMOS33;
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NET "din_miso" IOSTANDARD = LVCMOS33;
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NET "led_confok" IOSTANDARD = LVCMOS33;
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NET "led_fail" IOSTANDARD = LVCMOS33;
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NET "led_run" IOSTANDARD = LVCMOS33;
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NET "ls485_de1" IOSTANDARD = LVCMOS33;
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NET "ls485_de2" IOSTANDARD = LVCMOS33;
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NET "ls485_ren1" IOSTANDARD = LVCMOS33;
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NET "ls485_ren2" IOSTANDARD = LVCMOS33;
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NET "ls485_rx1" IOSTANDARD = LVCMOS33;
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NET "ls485_rx2" IOSTANDARD = LVCMOS33;
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NET "ls485_tx1" IOSTANDARD = LVCMOS33;
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NET "ls485_tx2" IOSTANDARD = LVCMOS33;
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NET "mosi" IOSTANDARD = LVCMOS33;
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NET "pic_rx" IOSTANDARD = LVCMOS33;
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NET "pic_sclk" IOSTANDARD = LVCMOS33;
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NET "pic_sdi" IOSTANDARD = LVCMOS33;
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NET "pic_sdo" IOSTANDARD = LVCMOS33;
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NET "pic_spare[0]" IOSTANDARD = LVCMOS33;
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NET "pic_spare[1]" IOSTANDARD = LVCMOS33;
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NET "pic_spare[2]" IOSTANDARD = LVCMOS33;
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NET "pic_spare[3]" IOSTANDARD = LVCMOS33;
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NET "pic_ssn" IOSTANDARD = LVCMOS33;
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NET "pic_tx" IOSTANDARD = LVCMOS33;
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NET "power_rstn" IOSTANDARD = LVCMOS33;
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NET "prog_b" IOSTANDARD = LVCMOS33;
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NET "rst_fpgan" IOSTANDARD = LVCMOS33;
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NET "rst_n" IOSTANDARD = LVCMOS33;
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NET "spare[0]" IOSTANDARD = LVCMOS33;
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NET "spare[1]" IOSTANDARD = LVCMOS33;
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NET "spare[2]" IOSTANDARD = LVCMOS33;
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NET "spare[3]" IOSTANDARD = LVCMOS33;
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NET "spare[4]" IOSTANDARD = LVCMOS33;
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NET "spare[5]" IOSTANDARD = LVCMOS33;
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NET "spare[6]" IOSTANDARD = LVCMOS33;
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NET "spare[7]" IOSTANDARD = LVCMOS33;
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NET "tp7" IOSTANDARD = LVCMOS33;
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NET "tp8" IOSTANDARD = LVCMOS33;
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NET "tp9" IOSTANDARD = LVCMOS33;
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NET "wp_flashn" IOSTANDARD = LVCMOS33;
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NET "pic_refclki" IOSTANDARD = LVCMOS33;

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