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[/] [saturn/] [trunk/] [IPCommunication/] [communication_sil.vhd] - Blame information for rev 2

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--============================================================================= 
--  TITRE : COMMUNICATION_SIL
--  DESCRIPTION : 
--        Impl�mente la pile communication des MIO s�curitaire
--  FICHIER :        communication_sil.vhd 
--=============================================================================
--  CREATION 
--  DATE              AUTEUR    PROJET  REVISION 
--  10/04/2014  DRA        SATURN       V1.0 
--=============================================================================
--  HISTORIQUE  DES  MODIFICATIONS :
--  DATE              AUTEUR    PROJET  REVISION 
--  18/09/14   DRA      SATURN   1.1
--    Evolution du module switch (prise en compte du signal SW_ENA) 
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
ENTITY communication_sil IS
   PORT (
      -- Ports syst�me
      clk_sys  : IN  STD_LOGIC;     -- Clock syst�me
      rst_n    : IN  STD_LOGIC;     -- Reset g�n�ral syst�me
      ad_mio   : IN  STD_LOGIC_VECTOR(7 DOWNTO 0); -- TID du MIO
 
      -- Interfaces s�ries 1 et 2
      rx1       : IN  STD_LOGIC;    -- R�ception s�rie port 1
      tx1       : OUT STD_LOGIC;    -- Transmission s�rie port 1
      rx2       : IN  STD_LOGIC;    -- R�ception s�rie port 2
      tx2       : OUT STD_LOGIC;    -- Transmission s�rie port 2
 
      copy_ena1 : IN  STD_LOGIC;    -- Autorise la copy du port 1 sur le port 2
      copy_ena2 : IN  STD_LOGIC;    -- Autorise la copy du port 2 sur le port 1
 
      -- Interfaces de lecture des trames port 1
      layer7_rx1       : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Donn�es applicatives re�ues sur port 1
      layer7_soc1      : OUT STD_LOGIC;         -- Indique un d�but de trame
      layer7_rd1       : IN  STD_LOGIC;         -- Signal de lecture d'un octet de plus
      layer7_newframe1 : OUT STD_LOGIC;         -- Indique la r�ception d'une nouvelle trame
      layer7_comdispo1 : OUT STD_LOGIC;         -- Indique qu'au moins une trame est dispo en m�moire
      layer7_l2ok1     : OUT STD_LOGIC;         -- Indique que la trame re�ue est conforme
      layer7_overflow1 : OUT STD_LOGIC;         -- Indique un d�bordement de m�moire
      activity1        : OUT STD_LOGIC;         -- Indique du trafic sur le port 1
 
      -- Interfaces de lecture des trames port 2
      layer7_rx2       : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Idem port 1
      layer7_soc2      : OUT STD_LOGIC;
      layer7_rd2       : IN  STD_LOGIC;
      layer7_newframe2 : OUT STD_LOGIC;
      layer7_comdispo2 : OUT STD_LOGIC;
      layer7_l2ok2     : OUT STD_LOGIC;
      layer7_overflow2 : OUT STD_LOGIC;
      activity2        : OUT STD_LOGIC;         -- Indique du trafic sur le port 2
 
      -- Interface d'�criture des trames
      tx_dat           : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Flux de donn�es applicatives � transmettre
      val_txdat        : IN  STD_LOGIC;         -- Indique un octet dispo sur tx_dat
      tx_sof           : IN  STD_LOGIC;         -- Indique un d�but de trame
      tx_eof           : IN  STD_LOGIC;         -- Indique une fin de trame
      txdat_free       : OUT STD_LOGIC;         -- Indique que le module couche transport Tx est dispo
      clr_fifo_tx      : IN  STD_LOGIC          -- Clear de la FIFO transport Tx
      );
END communication_sil;
 
ARCHITECTURE rtl of communication_sil is
   -- D�finit le nombre de bit n�cessaires pour mesurer la dur�e du bit le plus lent avec l'horloge syst�me
   -- i.e. 1 Bit � 50Kbit/s = 20�s nbbit_div = Log2(96MHz x 20�s)
   CONSTANT nbbit_div      : INTEGER := 11;
 
   -- DFF pour la m�tastabilit� de rx1 et rx2
   SIGNAL rx1_r1, rx1_r2 : STD_LOGIC;
   SIGNAL rx2_r1, rx2_r2 : STD_LOGIC;
 
   -- Diviseur d'horloge pour le baud rate
   SIGNAL tc_divclk     : STD_LOGIC_VECTOR(nbbit_div - 1 DOWNTO 0);  -- Termianl count du diviseur
   SIGNAL baud_locked   : STD_LOGIC;                                 -- Indique que l'autobaud est lock�
 
   -- Interfaces du SWITCH1
   SIGNAL layer1_rx1    : STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Flux de donn�e d�serialis� (Rx)
   SIGNAL layer1_val1   : STD_LOGIC;                     -- Indique un octet valide sur layer1_rx1
   SIGNAL sw_ena1       : STD_LOGIC;                     -- Indique qu'on est en r�ception entre 2 trames sur port 1
   SIGNAL layer1_tx1    : STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Flux de donn�e � s�rialiser (Tx)
   SIGNAL layer1_rd1    : STD_LOGIC;                     -- Demande un octet de plus � transmettre
   SIGNAL layer1_empty1 : STD_LOGIC;                     -- Indique qu'aucun octet n'est en attente de serialsiation
 
   -- Interfaces du SWITCH2
   SIGNAL layer1_rx2    : STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Idem port 1
   SIGNAL layer1_val2   : STD_LOGIC;
   SIGNAL sw_ena2       : STD_LOGIC;
   SIGNAL layer1_tx2    : STD_LOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL layer1_rd2    : STD_LOGIC;
   SIGNAL layer1_empty2 : STD_LOGIC;
 
   -- Interfaces du module LAYER2_RX1
   SIGNAL layer2_rx1    : STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Flux de donn�es applicatives destuff�
   SIGNAL layer2_rxval1 : STD_LOGIC;                     -- Indique un octet valide sur layer2_rx1
   SIGNAL layer2_sof1   : STD_LOGIC;                     -- Indique un  d�but de trame
   SIGNAL layer2_eof1   : STD_LOGIC;                     -- Indqiue une fin de trame
   SIGNAL layer2_l2ok1  : STD_LOGIC;                     -- Indique que la trame re�ue est correcte
 
   -- Interfaces du module LAYER2_RX2
   SIGNAL layer2_rx2    : STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Idem que port 1
   SIGNAL layer2_rxval2 : STD_LOGIC;
   SIGNAL layer2_sof2   : STD_LOGIC;
   SIGNAL layer2_eof2   : STD_LOGIC;
   SIGNAL layer2_l2ok2  : STD_LOGIC;
 
   -- Interfaces du module LAYER2_TX
   SIGNAL layer2_txdat     : STD_LOGIC_VECTOR(7 DOWNTO 0);-- Flux de donn�e stuff� + CRC transport
   SIGNAL layer2_txval     : STD_LOGIC;                  -- Indique un octet valide sur layer2_txdat
   SIGNAL layer2_progfull1 : STD_LOGIC;                  -- La FIFO de donn�es Tx port 1 est presque pleine
   SIGNAL layer2_progfull2 : STD_LOGIC;                  -- La FIFO de donn�es Tx port 2 est presque pleine
   SIGNAL layer2_full1     : STD_LOGIC;                  -- La FIFO de donn�es Tx port 1 est pleine
   SIGNAL layer2_full2     : STD_LOGIC;                  -- La FIFO de donn�es Tx port 2 est pleine
 
        COMPONENT autobaud
        PORT(
                clk_sys     : IN STD_LOGIC;
                rst_n       : IN STD_LOGIC;
                rx1         : IN STD_LOGIC;
                val_rx1     : IN STD_LOGIC;
                eof1        : IN STD_LOGIC;
                dat_rx1     : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
      l2_ok1      : IN STD_LOGIC;
                rx2         : IN STD_LOGIC;
                val_rx2     : IN STD_LOGIC;
                eof2        : IN STD_LOGIC;
                dat_rx2     : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
      l2_ok2      : IN STD_LOGIC;
                tc_divclk   : OUT STD_LOGIC_VECTOR(10 downto 0);
                baud_locked : OUT STD_LOGIC
                );
        END COMPONENT;
 
        COMPONENT switch
   GENERIC (
      nbbit_div : INTEGER := 10);
        PORT(
                clk_sys     : IN STD_LOGIC;
                rst_n       : IN STD_LOGIC;
      baud_lock   : IN  STD_LOGIC;
                tc_divclk   : IN STD_LOGIC_VECTOR(nbbit_div-1 downto 0);
                rx          : IN STD_LOGIC;
                rx_dat      : OUT STD_LOGIC_VECTOR(7 downto 0);
                rx_val      : OUT STD_LOGIC;
                tx          : OUT STD_LOGIC;
                tx_dat      : IN STD_LOGIC_VECTOR(7 downto 0);
                tx_rd       : OUT STD_LOGIC;
                tx_empty    : IN STD_LOGIC;
                sw_ena      : IN STD_LOGIC;
                copy_ena    : IN STD_LOGIC;
      etat                 : OUT  STD_LOGIC
                );
        END COMPONENT;
 
        COMPONENT layer2_rx
   GENERIC (
      nbbit_div : INTEGER := 10);
        PORT(
                clk_sys     : IN STD_LOGIC;
                rst_n       : IN STD_LOGIC;
                tc_divclk   : IN STD_LOGIC_VECTOR(nbbit_div-1 downto 0);
                ad_mio      : IN STD_LOGIC_VECTOR(7 downto 0);
                dat_in      : IN STD_LOGIC_VECTOR(7 downto 0);
                val_in      : IN STD_LOGIC;
                dat_out     : OUT STD_LOGIC_VECTOR(7 downto 0);
                val_out     : OUT STD_LOGIC;
                sw_ena      : OUT STD_LOGIC;
                sof         : OUT STD_LOGIC;
                eof         : OUT STD_LOGIC;
                l2_ok       : OUT STD_LOGIC
                );
        END COMPONENT;
 
        COMPONENT frame_store
        PORT(
                clk_sys     : IN STD_LOGIC;
                rst_n       : IN STD_LOGIC;
                dat_in      : IN STD_LOGIC_VECTOR(7 downto 0);
                val_in      : IN STD_LOGIC;
                sof         : IN STD_LOGIC;
                eof         : IN STD_LOGIC;
                l2_ok       : IN STD_LOGIC;
                dat_out     : OUT STD_LOGIC_VECTOR(7 downto 0);
      soc_out     : OUT STD_LOGIC;
                rd_datout   : IN STD_LOGIC;
                new_frame   : OUT STD_LOGIC;
                com_dispo   : OUT STD_LOGIC;
                l7_ok       : OUT STD_LOGIC;
      overflow    : OUT STD_LOGIC
                );
        END COMPONENT;
 
   COMPONENT layer2_tx
   PORT(
      clk_sys     : IN STD_LOGIC;
      rst_n       : IN STD_LOGIC;
      dat_in      : IN STD_LOGIC_VECTOR(7 downto 0);
      val_in      : IN STD_LOGIC;
      sof         : IN STD_LOGIC;
      eof         : IN STD_LOGIC;
      datin_free  : OUT STD_LOGIC;
      dat_out     : OUT STD_LOGIC_VECTOR(7 downto 0);
      val_out     : OUT STD_LOGIC;
      clr_fifo    : IN   STD_LOGIC;
      progfull1   : IN   STD_LOGIC;
      progfull2   : IN   STD_LOGIC;
      full1       : IN   STD_LOGIC;
      empty1      : IN   STD_LOGIC;
      full2       : IN   STD_LOGIC;
      empty2      : IN   STD_LOGIC
      );
   END COMPONENT;
 
   -- La FIFO contient 512 mots, le prog_full est configur� � 500 mots pour laisser une marge de 
   -- stockage avant overflow (voir le module layer2_tx)
   COMPONENT fifo_tx
   PORT (
      clk      : IN STD_LOGIC;
      srst     : IN STD_LOGIC;
      din      : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
      wr_en    : IN STD_LOGIC;
      rd_en    : IN STD_LOGIC;
      dout     : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
      full     : OUT STD_LOGIC;
      empty    : OUT STD_LOGIC;
      prog_full: OUT STD_LOGIC
      );
   END COMPONENT;
 
BEGIN
   --------------------------------------------
   -- Gestion de la m�tastbilit� de rx1 et rx2
   --------------------------------------------
   meta : PROCESS(clk_sys, rst_n)
   BEGIN
      IF (rst_n = '0') THEN
         rx1_r1 <= '1';
         rx1_r2 <= '1';
         rx2_r1 <= '1';
         rx2_r2 <= '1';
      ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
         rx1_r1 <= rx1;
         rx1_r2 <= rx1_r1;
         rx2_r1 <= rx2;
         rx2_r2 <= rx2_r1;
      END IF;
   END PROCESS;
 
        inst_autobaud: autobaud
   PORT MAP(
                clk_sys =>  clk_sys,
                rst_n =>    rst_n,
                rx1 =>      rx1_r2,
                rx2 =>      rx2_r2,
                val_rx1 =>  layer1_val1,
                dat_rx1 =>  layer1_rx1,
      eof1 =>     layer2_eof1,
                l2_ok1 =>   layer2_l2ok1,
                val_rx2 =>  layer1_val2,
      dat_rx2 =>  layer1_rx2,
                eof2 =>     layer2_eof2,
                l2_ok2 =>   layer2_l2ok2,
                tc_divclk => tc_divclk,
                baud_locked => baud_locked
        );
 
        inst_switch1: switch
   GENERIC MAP (
      nbbit_div => nbbit_div)
   PORT MAP(
                clk_sys =>     clk_sys,
                rst_n =>       rst_n,
      baud_lock =>   baud_locked,
                tc_divclk =>   tc_divclk,
                rx =>          rx1_r2,
                rx_dat =>      layer1_rx1,
                rx_val =>      layer1_val1,
                tx =>          tx2,
                tx_dat =>      layer1_tx2,
                tx_rd =>       layer1_rd2,
                tx_empty =>    layer1_empty2,
                sw_ena =>      sw_ena1,
                copy_ena =>    copy_ena1,
      etat =>        OPEN
        );
 
        inst_switch2: switch
   GENERIC MAP (
      nbbit_div => nbbit_div)
   PORT MAP(
                clk_sys =>     clk_sys,
                rst_n =>       rst_n,
      baud_lock =>   baud_locked,
                tc_divclk =>   tc_divclk,
                rx =>          rx2_r2,
                rx_dat =>      layer1_rx2,
                rx_val =>      layer1_val2,
                tx =>          tx1,
                tx_dat =>      layer1_tx1,
                tx_rd =>       layer1_rd1,
                tx_empty =>    layer1_empty1,
                sw_ena =>      sw_ena2,
                copy_ena =>    copy_ena2,
      etat =>        OPEN
        );
 
        inst_layer2_rx1: layer2_rx
   GENERIC MAP (
      nbbit_div => nbbit_div)
   PORT MAP(
                clk_sys =>     clk_sys,
                rst_n =>       rst_n,
                tc_divclk =>   tc_divclk,
      ad_mio =>      ad_mio,
                dat_in =>      layer1_rx1,
                val_in =>      layer1_val1,
                dat_out =>     layer2_rx1,
                val_out =>     layer2_rxval1,
                sof =>         layer2_sof1,
                eof =>         layer2_eof1,
                l2_ok =>       layer2_l2ok1,
                sw_ena =>      sw_ena1
        );
   activity1 <= layer2_eof1;
 
        inst_layer2_rx2: layer2_rx
   GENERIC MAP (
      nbbit_div => nbbit_div)
   PORT MAP(
                clk_sys =>     clk_sys,
                rst_n =>       rst_n,
                tc_divclk =>   tc_divclk,
      ad_mio =>      ad_mio,
                dat_in =>      layer1_rx2,
                val_in =>      layer1_val2,
                dat_out =>     layer2_rx2,
                val_out =>     layer2_rxval2,
                sof =>         layer2_sof2,
                eof =>         layer2_eof2,
                l2_ok =>       layer2_l2ok2,
                sw_ena =>      sw_ena2
        );
   activity2 <= layer2_eof2;
 
        inst_frame_store1: frame_store
   PORT MAP(
                clk_sys =>     clk_sys,
                rst_n =>       rst_n,
                dat_in =>      layer2_rx1,
                val_in =>      layer2_rxval1,
                sof =>         layer2_sof1,
                eof =>         layer2_eof1,
                l2_ok =>       layer2_l2ok1,
                dat_out =>     layer7_rx1,
      soc_out =>     layer7_soc1,
                rd_datout =>   layer7_rd1,
                new_frame =>   layer7_newframe1,
                com_dispo =>   layer7_comdispo1,
                l7_ok =>       layer7_l2ok1,
      overflow =>    layer7_overflow1
        );
 
        inst_frame_store2: frame_store
   PORT MAP(
                clk_sys =>     clk_sys,
                rst_n =>       rst_n,
                dat_in =>      layer2_rx2,
                val_in =>      layer2_rxval2,
                sof =>         layer2_sof2,
                eof =>         layer2_eof2,
                l2_ok =>       layer2_l2ok2,
                dat_out =>     layer7_rx2,
      soc_out =>     layer7_soc2,
                rd_datout =>   layer7_rd2,
                new_frame =>   layer7_newframe2,
                com_dispo =>   layer7_comdispo2,
                l7_ok =>       layer7_l2ok2,
      overflow =>    layer7_overflow2
        );
 
   inst_layer2_tx: layer2_tx
   PORT MAP(
      clk_sys => clk_sys,
      rst_n => rst_n,
      dat_in => tx_dat,
      val_in => val_txdat,
      sof => tx_sof,
      eof => tx_eof,
      datin_free => txdat_free,
      dat_out => layer2_txdat,
      val_out => layer2_txval,
      clr_fifo => clr_fifo_tx,
      progfull1 => layer2_progfull1,
      progfull2 => layer2_progfull2,
      full1     => layer2_full1,
      empty1    => layer1_empty1,
      full2     => layer2_full2,
      empty2    => layer1_empty2
        );
 
   inst_fifo_tx1 : fifo_tx
   PORT MAP (
      clk =>   clk_sys,
      srst =>  clr_fifo_tx,
      din =>   layer2_txdat,
      wr_en => layer2_txval,
      rd_en => layer1_rd1,
      dout =>  layer1_tx1,
      full =>  layer2_full1,
      empty => layer1_empty1,
      prog_full => layer2_progfull1
   );
 
   inst_fifo_tx2 : fifo_tx
   PORT MAP (
      clk =>   clk_sys,
      srst =>  clr_fifo_tx,
      din =>   layer2_txdat,
      wr_en => layer2_txval,
      rd_en => layer1_rd2,
      dout =>  layer1_tx2,
      full =>  layer2_full2,
      empty => layer1_empty2,
      prog_full => layer2_progfull2
   );
 
END rtl;
 

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Subversion Repositories saturn

[/] [saturn/] [trunk/] [IPCommunication/] [communication_sil.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	DavidRAMBA	`--=============================================================================`
2			`-- TITRE : COMMUNICATION_SIL`
3			`-- DESCRIPTION :`
4			`-- Impl�mente la pile communication des MIO s�curitaire`
5			`-- FICHIER : communication_sil.vhd`
6			`--=============================================================================`
7			`-- CREATION`
8			`-- DATE AUTEUR PROJET REVISION`
9			`-- 10/04/2014 DRA SATURN V1.0`
10			`--=============================================================================`
11			`-- HISTORIQUE DES MODIFICATIONS :`
12			`-- DATE AUTEUR PROJET REVISION`
13			`-- 18/09/14 DRA SATURN 1.1`
14			`-- Evolution du module switch (prise en compte du signal SW_ENA)`
15			`--=============================================================================`
16
17			`LIBRARY IEEE;`
18			`USE IEEE.STD_LOGIC_1164.ALL;`
19			`USE IEEE.STD_LOGIC_ARITH.ALL;`
20			`USE IEEE.STD_LOGIC_UNSIGNED.ALL;`
21
22			`ENTITY communication_sil IS`
23			`PORT (`
24			`-- Ports syst�me`
25			`clk_sys : IN STD_LOGIC; -- Clock syst�me`
26			`rst_n : IN STD_LOGIC; -- Reset g�n�ral syst�me`
27			`ad_mio : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- TID du MIO`
28
29			`-- Interfaces s�ries 1 et 2`
30			`rx1 : IN STD_LOGIC; -- R�ception s�rie port 1`
31			`tx1 : OUT STD_LOGIC; -- Transmission s�rie port 1`
32			`rx2 : IN STD_LOGIC; -- R�ception s�rie port 2`
33			`tx2 : OUT STD_LOGIC; -- Transmission s�rie port 2`
34
35			`copy_ena1 : IN STD_LOGIC; -- Autorise la copy du port 1 sur le port 2`
36			`copy_ena2 : IN STD_LOGIC; -- Autorise la copy du port 2 sur le port 1`
37
38			`-- Interfaces de lecture des trames port 1`
39			`layer7_rx1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Donn�es applicatives re�ues sur port 1`
40			`layer7_soc1 : OUT STD_LOGIC; -- Indique un d�but de trame`
41			`layer7_rd1 : IN STD_LOGIC; -- Signal de lecture d'un octet de plus`
42			`layer7_newframe1 : OUT STD_LOGIC; -- Indique la r�ception d'une nouvelle trame`
43			`layer7_comdispo1 : OUT STD_LOGIC; -- Indique qu'au moins une trame est dispo en m�moire`
44			`layer7_l2ok1 : OUT STD_LOGIC; -- Indique que la trame re�ue est conforme`
45			`layer7_overflow1 : OUT STD_LOGIC; -- Indique un d�bordement de m�moire`
46			`activity1 : OUT STD_LOGIC; -- Indique du trafic sur le port 1`
47
48			`-- Interfaces de lecture des trames port 2`
49			`layer7_rx2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem port 1`
50			`layer7_soc2 : OUT STD_LOGIC;`
51			`layer7_rd2 : IN STD_LOGIC;`
52			`layer7_newframe2 : OUT STD_LOGIC;`
53			`layer7_comdispo2 : OUT STD_LOGIC;`
54			`layer7_l2ok2 : OUT STD_LOGIC;`
55			`layer7_overflow2 : OUT STD_LOGIC;`
56			`activity2 : OUT STD_LOGIC; -- Indique du trafic sur le port 2`
57
58			`-- Interface d'�criture des trames`
59			`tx_dat : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Flux de donn�es applicatives � transmettre`
60			`val_txdat : IN STD_LOGIC; -- Indique un octet dispo sur tx_dat`
61			`tx_sof : IN STD_LOGIC; -- Indique un d�but de trame`
62			`tx_eof : IN STD_LOGIC; -- Indique une fin de trame`
63			`txdat_free : OUT STD_LOGIC; -- Indique que le module couche transport Tx est dispo`
64			`clr_fifo_tx : IN STD_LOGIC -- Clear de la FIFO transport Tx`
65			`);`
66			`END communication_sil;`
67
68			`ARCHITECTURE rtl of communication_sil is`
69			`-- D�finit le nombre de bit n�cessaires pour mesurer la dur�e du bit le plus lent avec l'horloge syst�me`
70			`-- i.e. 1 Bit � 50Kbit/s = 20�s nbbit_div = Log2(96MHz x 20�s)`
71			`CONSTANT nbbit_div : INTEGER := 11;`
72
73			`-- DFF pour la m�tastabilit� de rx1 et rx2`
74			`SIGNAL rx1_r1, rx1_r2 : STD_LOGIC;`
75			`SIGNAL rx2_r1, rx2_r2 : STD_LOGIC;`
76
77			`-- Diviseur d'horloge pour le baud rate`
78			`SIGNAL tc_divclk : STD_LOGIC_VECTOR(nbbit_div - 1 DOWNTO 0); -- Termianl count du diviseur`
79			`SIGNAL baud_locked : STD_LOGIC; -- Indique que l'autobaud est lock�`
80
81			`-- Interfaces du SWITCH1`
82			`SIGNAL layer1_rx1 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Flux de donn�e d�serialis� (Rx)`
83			`SIGNAL layer1_val1 : STD_LOGIC; -- Indique un octet valide sur layer1_rx1`
84			`SIGNAL sw_ena1 : STD_LOGIC; -- Indique qu'on est en r�ception entre 2 trames sur port 1`
85			`SIGNAL layer1_tx1 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Flux de donn�e � s�rialiser (Tx)`
86			`SIGNAL layer1_rd1 : STD_LOGIC; -- Demande un octet de plus � transmettre`
87			`SIGNAL layer1_empty1 : STD_LOGIC; -- Indique qu'aucun octet n'est en attente de serialsiation`
88
89			`-- Interfaces du SWITCH2`
90			`SIGNAL layer1_rx2 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem port 1`
91			`SIGNAL layer1_val2 : STD_LOGIC;`
92			`SIGNAL sw_ena2 : STD_LOGIC;`
93			`SIGNAL layer1_tx2 : STD_LOGIC_VECTOR(7 DOWNTO 0);`
94			`SIGNAL layer1_rd2 : STD_LOGIC;`
95			`SIGNAL layer1_empty2 : STD_LOGIC;`
96
97			`-- Interfaces du module LAYER2_RX1`
98			`SIGNAL layer2_rx1 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Flux de donn�es applicatives destuff�`
99			`SIGNAL layer2_rxval1 : STD_LOGIC; -- Indique un octet valide sur layer2_rx1`
100			`SIGNAL layer2_sof1 : STD_LOGIC; -- Indique un d�but de trame`
101			`SIGNAL layer2_eof1 : STD_LOGIC; -- Indqiue une fin de trame`
102			`SIGNAL layer2_l2ok1 : STD_LOGIC; -- Indique que la trame re�ue est correcte`
103
104			`-- Interfaces du module LAYER2_RX2`
105			`SIGNAL layer2_rx2 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem que port 1`
106			`SIGNAL layer2_rxval2 : STD_LOGIC;`
107			`SIGNAL layer2_sof2 : STD_LOGIC;`
108			`SIGNAL layer2_eof2 : STD_LOGIC;`
109			`SIGNAL layer2_l2ok2 : STD_LOGIC;`
110
111			`-- Interfaces du module LAYER2_TX`
112			`SIGNAL layer2_txdat : STD_LOGIC_VECTOR(7 DOWNTO 0);-- Flux de donn�e stuff� + CRC transport`
113			`SIGNAL layer2_txval : STD_LOGIC; -- Indique un octet valide sur layer2_txdat`
114			`SIGNAL layer2_progfull1 : STD_LOGIC; -- La FIFO de donn�es Tx port 1 est presque pleine`
115			`SIGNAL layer2_progfull2 : STD_LOGIC; -- La FIFO de donn�es Tx port 2 est presque pleine`
116			`SIGNAL layer2_full1 : STD_LOGIC; -- La FIFO de donn�es Tx port 1 est pleine`
117			`SIGNAL layer2_full2 : STD_LOGIC; -- La FIFO de donn�es Tx port 2 est pleine`
118
119			`COMPONENT autobaud`
120			`PORT(`
121			`clk_sys : IN STD_LOGIC;`
122			`rst_n : IN STD_LOGIC;`
123			`rx1 : IN STD_LOGIC;`
124			`val_rx1 : IN STD_LOGIC;`
125			`eof1 : IN STD_LOGIC;`
126			`dat_rx1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
127			`l2_ok1 : IN STD_LOGIC;`
128			`rx2 : IN STD_LOGIC;`
129			`val_rx2 : IN STD_LOGIC;`
130			`eof2 : IN STD_LOGIC;`
131			`dat_rx2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
132			`l2_ok2 : IN STD_LOGIC;`
133			`tc_divclk : OUT STD_LOGIC_VECTOR(10 downto 0);`
134			`baud_locked : OUT STD_LOGIC`
135			`);`
136			`END COMPONENT;`
137
138			`COMPONENT switch`
139			`GENERIC (`
140			`nbbit_div : INTEGER := 10);`
141			`PORT(`
142			`clk_sys : IN STD_LOGIC;`
143			`rst_n : IN STD_LOGIC;`
144			`baud_lock : IN STD_LOGIC;`
145			`tc_divclk : IN STD_LOGIC_VECTOR(nbbit_div-1 downto 0);`
146			`rx : IN STD_LOGIC;`
147			`rx_dat : OUT STD_LOGIC_VECTOR(7 downto 0);`
148			`rx_val : OUT STD_LOGIC;`
149			`tx : OUT STD_LOGIC;`
150			`tx_dat : IN STD_LOGIC_VECTOR(7 downto 0);`
151			`tx_rd : OUT STD_LOGIC;`
152			`tx_empty : IN STD_LOGIC;`
153			`sw_ena : IN STD_LOGIC;`
154			`copy_ena : IN STD_LOGIC;`
155			`etat : OUT STD_LOGIC`
156			`);`
157			`END COMPONENT;`
158
159			`COMPONENT layer2_rx`
160			`GENERIC (`
161			`nbbit_div : INTEGER := 10);`
162			`PORT(`
163			`clk_sys : IN STD_LOGIC;`
164			`rst_n : IN STD_LOGIC;`
165			`tc_divclk : IN STD_LOGIC_VECTOR(nbbit_div-1 downto 0);`
166			`ad_mio : IN STD_LOGIC_VECTOR(7 downto 0);`
167			`dat_in : IN STD_LOGIC_VECTOR(7 downto 0);`
168			`val_in : IN STD_LOGIC;`
169			`dat_out : OUT STD_LOGIC_VECTOR(7 downto 0);`
170			`val_out : OUT STD_LOGIC;`
171			`sw_ena : OUT STD_LOGIC;`
172			`sof : OUT STD_LOGIC;`
173			`eof : OUT STD_LOGIC;`
174			`l2_ok : OUT STD_LOGIC`
175			`);`
176			`END COMPONENT;`
177
178			`COMPONENT frame_store`
179			`PORT(`
180			`clk_sys : IN STD_LOGIC;`
181			`rst_n : IN STD_LOGIC;`
182			`dat_in : IN STD_LOGIC_VECTOR(7 downto 0);`
183			`val_in : IN STD_LOGIC;`
184			`sof : IN STD_LOGIC;`
185			`eof : IN STD_LOGIC;`
186			`l2_ok : IN STD_LOGIC;`
187			`dat_out : OUT STD_LOGIC_VECTOR(7 downto 0);`
188			`soc_out : OUT STD_LOGIC;`
189			`rd_datout : IN STD_LOGIC;`
190			`new_frame : OUT STD_LOGIC;`
191			`com_dispo : OUT STD_LOGIC;`
192			`l7_ok : OUT STD_LOGIC;`
193			`overflow : OUT STD_LOGIC`
194			`);`
195			`END COMPONENT;`
196
197			`COMPONENT layer2_tx`
198			`PORT(`
199			`clk_sys : IN STD_LOGIC;`
200			`rst_n : IN STD_LOGIC;`
201			`dat_in : IN STD_LOGIC_VECTOR(7 downto 0);`
202			`val_in : IN STD_LOGIC;`
203			`sof : IN STD_LOGIC;`
204			`eof : IN STD_LOGIC;`
205			`datin_free : OUT STD_LOGIC;`
206			`dat_out : OUT STD_LOGIC_VECTOR(7 downto 0);`
207			`val_out : OUT STD_LOGIC;`
208			`clr_fifo : IN STD_LOGIC;`
209			`progfull1 : IN STD_LOGIC;`
210			`progfull2 : IN STD_LOGIC;`
211			`full1 : IN STD_LOGIC;`
212			`empty1 : IN STD_LOGIC;`
213			`full2 : IN STD_LOGIC;`
214			`empty2 : IN STD_LOGIC`
215			`);`
216			`END COMPONENT;`
217
218			`-- La FIFO contient 512 mots, le prog_full est configur� � 500 mots pour laisser une marge de`
219			`-- stockage avant overflow (voir le module layer2_tx)`
220			`COMPONENT fifo_tx`
221			`PORT (`
222			`clk : IN STD_LOGIC;`
223			`srst : IN STD_LOGIC;`
224			`din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
225			`wr_en : IN STD_LOGIC;`
226			`rd_en : IN STD_LOGIC;`
227			`dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
228			`full : OUT STD_LOGIC;`
229			`empty : OUT STD_LOGIC;`
230			`prog_full: OUT STD_LOGIC`
231			`);`
232			`END COMPONENT;`
233
234			`BEGIN`
235			`--------------------------------------------`
236			`-- Gestion de la m�tastbilit� de rx1 et rx2`
237			`--------------------------------------------`
238			`meta : PROCESS(clk_sys, rst_n)`
239			`BEGIN`
240			`IF (rst_n = '0') THEN`
241			`rx1_r1 <= '1';`
242			`rx1_r2 <= '1';`
243			`rx2_r1 <= '1';`
244			`rx2_r2 <= '1';`
245			`ELSIF (clk_sys'EVENT and clk_sys = '1') THEN`
246			`rx1_r1 <= rx1;`
247			`rx1_r2 <= rx1_r1;`
248			`rx2_r1 <= rx2;`
249			`rx2_r2 <= rx2_r1;`
250			`END IF;`
251			`END PROCESS;`
252
253			`inst_autobaud: autobaud`
254			`PORT MAP(`
255			`clk_sys => clk_sys,`
256			`rst_n => rst_n,`
257			`rx1 => rx1_r2,`
258			`rx2 => rx2_r2,`
259			`val_rx1 => layer1_val1,`
260			`dat_rx1 => layer1_rx1,`
261			`eof1 => layer2_eof1,`
262			`l2_ok1 => layer2_l2ok1,`
263			`val_rx2 => layer1_val2,`
264			`dat_rx2 => layer1_rx2,`
265			`eof2 => layer2_eof2,`
266			`l2_ok2 => layer2_l2ok2,`
267			`tc_divclk => tc_divclk,`
268			`baud_locked => baud_locked`
269			`);`
270
271			`inst_switch1: switch`
272			`GENERIC MAP (`
273			`nbbit_div => nbbit_div)`
274			`PORT MAP(`
275			`clk_sys => clk_sys,`
276			`rst_n => rst_n,`
277			`baud_lock => baud_locked,`
278			`tc_divclk => tc_divclk,`
279			`rx => rx1_r2,`
280			`rx_dat => layer1_rx1,`
281			`rx_val => layer1_val1,`
282			`tx => tx2,`
283			`tx_dat => layer1_tx2,`
284			`tx_rd => layer1_rd2,`
285			`tx_empty => layer1_empty2,`
286			`sw_ena => sw_ena1,`
287			`copy_ena => copy_ena1,`
288			`etat => OPEN`
289			`);`
290
291			`inst_switch2: switch`
292			`GENERIC MAP (`
293			`nbbit_div => nbbit_div)`
294			`PORT MAP(`
295			`clk_sys => clk_sys,`
296			`rst_n => rst_n,`
297			`baud_lock => baud_locked,`
298			`tc_divclk => tc_divclk,`
299			`rx => rx2_r2,`
300			`rx_dat => layer1_rx2,`
301			`rx_val => layer1_val2,`
302			`tx => tx1,`
303			`tx_dat => layer1_tx1,`
304			`tx_rd => layer1_rd1,`
305			`tx_empty => layer1_empty1,`
306			`sw_ena => sw_ena2,`
307			`copy_ena => copy_ena2,`
308			`etat => OPEN`
309			`);`
310
311			`inst_layer2_rx1: layer2_rx`
312			`GENERIC MAP (`
313			`nbbit_div => nbbit_div)`
314			`PORT MAP(`
315			`clk_sys => clk_sys,`
316			`rst_n => rst_n,`
317			`tc_divclk => tc_divclk,`
318			`ad_mio => ad_mio,`
319			`dat_in => layer1_rx1,`
320			`val_in => layer1_val1,`
321			`dat_out => layer2_rx1,`
322			`val_out => layer2_rxval1,`
323			`sof => layer2_sof1,`
324			`eof => layer2_eof1,`
325			`l2_ok => layer2_l2ok1,`
326			`sw_ena => sw_ena1`
327			`);`
328			`activity1 <= layer2_eof1;`
329
330			`inst_layer2_rx2: layer2_rx`
331			`GENERIC MAP (`
332			`nbbit_div => nbbit_div)`
333			`PORT MAP(`
334			`clk_sys => clk_sys,`
335			`rst_n => rst_n,`
336			`tc_divclk => tc_divclk,`
337			`ad_mio => ad_mio,`
338			`dat_in => layer1_rx2,`
339			`val_in => layer1_val2,`
340			`dat_out => layer2_rx2,`
341			`val_out => layer2_rxval2,`
342			`sof => layer2_sof2,`
343			`eof => layer2_eof2,`
344			`l2_ok => layer2_l2ok2,`
345			`sw_ena => sw_ena2`
346			`);`
347			`activity2 <= layer2_eof2;`
348
349			`inst_frame_store1: frame_store`
350			`PORT MAP(`
351			`clk_sys => clk_sys,`
352			`rst_n => rst_n,`
353			`dat_in => layer2_rx1,`
354			`val_in => layer2_rxval1,`
355			`sof => layer2_sof1,`
356			`eof => layer2_eof1,`
357			`l2_ok => layer2_l2ok1,`
358			`dat_out => layer7_rx1,`
359			`soc_out => layer7_soc1,`
360			`rd_datout => layer7_rd1,`
361			`new_frame => layer7_newframe1,`
362			`com_dispo => layer7_comdispo1,`
363			`l7_ok => layer7_l2ok1,`
364			`overflow => layer7_overflow1`
365			`);`
366
367			`inst_frame_store2: frame_store`
368			`PORT MAP(`
369			`clk_sys => clk_sys,`
370			`rst_n => rst_n,`
371			`dat_in => layer2_rx2,`
372			`val_in => layer2_rxval2,`
373			`sof => layer2_sof2,`
374			`eof => layer2_eof2,`
375			`l2_ok => layer2_l2ok2,`
376			`dat_out => layer7_rx2,`
377			`soc_out => layer7_soc2,`
378			`rd_datout => layer7_rd2,`
379			`new_frame => layer7_newframe2,`
380			`com_dispo => layer7_comdispo2,`
381			`l7_ok => layer7_l2ok2,`
382			`overflow => layer7_overflow2`
383			`);`
384
385			`inst_layer2_tx: layer2_tx`
386			`PORT MAP(`
387			`clk_sys => clk_sys,`
388			`rst_n => rst_n,`
389			`dat_in => tx_dat,`
390			`val_in => val_txdat,`
391			`sof => tx_sof,`
392			`eof => tx_eof,`
393			`datin_free => txdat_free,`
394			`dat_out => layer2_txdat,`
395			`val_out => layer2_txval,`
396			`clr_fifo => clr_fifo_tx,`
397			`progfull1 => layer2_progfull1,`
398			`progfull2 => layer2_progfull2,`
399			`full1 => layer2_full1,`
400			`empty1 => layer1_empty1,`
401			`full2 => layer2_full2,`
402			`empty2 => layer1_empty2`
403			`);`
404
405			`inst_fifo_tx1 : fifo_tx`
406			`PORT MAP (`
407			`clk => clk_sys,`
408			`srst => clr_fifo_tx,`
409			`din => layer2_txdat,`
410			`wr_en => layer2_txval,`
411			`rd_en => layer1_rd1,`
412			`dout => layer1_tx1,`
413			`full => layer2_full1,`
414			`empty => layer1_empty1,`
415			`prog_full => layer2_progfull1`
416			`);`
417
418			`inst_fifo_tx2 : fifo_tx`
419			`PORT MAP (`
420			`clk => clk_sys,`
421			`srst => clr_fifo_tx,`
422			`din => layer2_txdat,`
423			`wr_en => layer2_txval,`
424			`rd_en => layer1_rd2,`
425			`dout => layer1_tx2,`
426			`full => layer2_full2,`
427			`empty => layer1_empty2,`
428			`prog_full => layer2_progfull2`
429			`);`
430
431			`END rtl;`
432