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--============================================================================= 
--  TITRE : COMMUNICATION_SIL4
--  DESCRIPTION : 
--        Impl�mente la pile communication des MIO s�curitaire pour un module SIL4
--  FICHIER :        communication_sil4.vhd 
--=============================================================================
--  CREATION 
--  DATE              AUTEUR    PROJET  REVISION 
--  10/04/2014  DRA        SATURN       V1.0 
--=============================================================================
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
ENTITY communication_sil4 IS
   PORT (
      -- Ports syst�me
      clk_sys  : IN  STD_LOGIC;     -- Clock syst�me
      rst_n    : IN  STD_LOGIC;     -- Reset g�n�ral syst�me
      ad_mio   : IN  STD_LOGIC_VECTOR(7 DOWNTO 0); -- TID du MIO
 
      -- Interfaces s�ries 1 et 2
      rx1       : IN  STD_LOGIC;    -- R�ception s�rie port 1
      tx1       : OUT STD_LOGIC;    -- Transmission s�rie port 1
      rx2       : IN  STD_LOGIC;    -- R�ception s�rie port 2
      tx2       : OUT STD_LOGIC;    -- Transmission s�rie port 2
 
      copy_ena1 : IN  STD_LOGIC;    -- Autorise la copy du port 1 sur le port 2
      copy_ena2 : IN  STD_LOGIC;    -- Autorise la copy du port 2 sur le port 1
 
      -- Interfaces de lecture des trames port 1 c�t� �C1
      layer7_rx1_uc1   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Donn�es applicatives re�ues sur port 1
      layer7_soc1_uc1  : OUT STD_LOGIC;         -- Indique un d�but de trame
      layer7_rd1_uc1   : IN  STD_LOGIC;         -- Signal de lecture d'un octet de plus
      layer7_newframe1_uc1 : OUT STD_LOGIC;     -- Indique la r�ception d'une nouvelle trame
      layer7_comdispo1_uc1 : OUT STD_LOGIC;     -- Indique qu'au moins une trame est dispo en m�moire
      layer7_l2ok1_uc1 : OUT STD_LOGIC;         -- Indique que la trame re�ue est conforme
      layer7_overflow1_uc1 : OUT STD_LOGIC;     -- Indique un d�bordement de m�moire
      activity1        : OUT STD_LOGIC;         -- Indique du trafic sur le port 1
      -- Interfaces de lecture des trames port 2 c�t� �C1
      layer7_rx2_uc1   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Idem port 1
      layer7_soc2_uc1  : OUT STD_LOGIC;
      layer7_rd2_uc1   : IN  STD_LOGIC;
      layer7_newframe2_uc1 : OUT STD_LOGIC;
      layer7_comdispo2_uc1 : OUT STD_LOGIC;
      layer7_l2ok2_uc1 : OUT STD_LOGIC;
      layer7_overflow2_uc1 : OUT STD_LOGIC;
      activity2        : OUT STD_LOGIC;         -- Indique du trafic sur le port 2
      -- Interfaces de lecture des trames port 1 c�t� �C1
      layer7_rx1_uc2   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Donn�es applicatives re�ues sur port 1
      layer7_soc1_uc2  : OUT STD_LOGIC;         -- Indique un d�but de trame
      layer7_rd1_uc2   : IN  STD_LOGIC;         -- Signal de lecture d'un octet de plus
      layer7_newframe1_uc2 : OUT STD_LOGIC;     -- Indique la r�ception d'une nouvelle trame
      layer7_comdispo1_uc2 : OUT STD_LOGIC;     -- Indique qu'au moins une trame est dispo en m�moire
      layer7_l2ok1_uc2 : OUT STD_LOGIC;         -- Indique que la trame re�ue est conforme
      layer7_overflow1_uc2 : OUT STD_LOGIC;     -- Indique un d�bordement de m�moire
      -- Interfaces de lecture des trames port 2 c�t� �C1
      layer7_rx2_uc2   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Idem port 1
      layer7_soc2_uc2  : OUT STD_LOGIC;
      layer7_rd2_uc2   : IN  STD_LOGIC;
      layer7_newframe2_uc2 : OUT STD_LOGIC;
      layer7_comdispo2_uc2 : OUT STD_LOGIC;
      layer7_l2ok2_uc2 : OUT STD_LOGIC;
      layer7_overflow2_uc2 : OUT STD_LOGIC;
      -- Interface d'�criture des trames c�t� �C1
      txdat_free       : OUT STD_LOGIC;         -- Indique que le module couche transport Tx est dispo
      tx_dat_uc1       : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Flux de donn�es applicatives � transmettre
      val_txdat_uc1    : IN  STD_LOGIC;         -- Indique un octet dispo sur tx_dat
      tx_sof_uc1       : IN  STD_LOGIC;         -- Indique un d�but de trame
      tx_eof_uc1       : IN  STD_LOGIC;         -- Indique une fin de trame
      clr_fifo_tx_uc1  : IN  STD_LOGIC;         -- Clear de la FIFO transport Tx
      -- Interface d'�criture des trames c�t� �C2
      tx_dat_uc2       : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Flux de donn�es applicatives � transmettre
      val_txdat_uc2    : IN  STD_LOGIC;         -- Indique un octet dispo sur tx_dat
      tx_sof_uc2       : IN  STD_LOGIC;         -- Indique un d�but de trame
      tx_eof_uc2       : IN  STD_LOGIC;         -- Indique une fin de trame
      clr_fifo_tx_uc2  : IN  STD_LOGIC          -- Clear de la FIFO transport Tx
      );
END communication_sil4;
 
ARCHITECTURE rtl of communication_sil4 is
   -- D�finit le nombre de bit n�cessaires pour mesurer la dur�e du bit le plus lent avec l'horloge syst�me
   -- i.e. 1 Bit � 50Kbit/s = 20�s nbbit_div = Log2(96MHz x 20�s)
   CONSTANT nbbit_div      : INTEGER := 11;
 
   -- DFF pour la m�tastabilit� de rx1 et rx2
   SIGNAL rx1_r1, rx1_r2 : STD_LOGIC;
   SIGNAL rx2_r1, rx2_r2 : STD_LOGIC;
 
   -- Diviseur d'horloge pour le baud rate
   SIGNAL tc_divclk     : STD_LOGIC_VECTOR(nbbit_div - 1 DOWNTO 0);  -- Termianl count du diviseur
   SIGNAL baud_locked   : STD_LOGIC;                                 -- Indique que l'autobaud est lock�
 
   -- Interfaces du SWITCH1
   SIGNAL layer1_rx1    : STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Flux de donn�e d�serialis� (Rx)
   SIGNAL layer1_val1   : STD_LOGIC;                     -- Indique un octet valide sur layer1_rx1
   SIGNAL sw_ena1       : STD_LOGIC;                     -- Indique qu'on est en r�ception entre 2 trames sur port 1
   SIGNAL layer1_tx1    : STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Flux de donn�e � s�rialiser (Tx)
   SIGNAL layer1_rd1    : STD_LOGIC;                     -- Demande un octet de plus � transmettre
   SIGNAL layer1_empty1 : STD_LOGIC;                     -- Indique qu'aucun octet n'est en attente de serialsiation
 
   -- Interfaces du SWITCH2
   SIGNAL layer1_rx2    : STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Idem port 1
   SIGNAL layer1_val2   : STD_LOGIC;
   SIGNAL sw_ena2       : STD_LOGIC;
   SIGNAL layer1_tx2    : STD_LOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL layer1_rd2    : STD_LOGIC;
   SIGNAL layer1_empty2 : STD_LOGIC;
 
   -- Interfaces du module LAYER2_RX1
   SIGNAL layer2_rx1    : STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Flux de donn�es applicatives destuff�
   SIGNAL layer2_rxval1 : STD_LOGIC;                     -- Indique un octet valide sur layer2_rx1
   SIGNAL layer2_sof1   : STD_LOGIC;                     -- Indique un  d�but de trame
   SIGNAL layer2_eof1   : STD_LOGIC;                     -- Indqiue une fin de trame
   SIGNAL layer2_l2ok1  : STD_LOGIC;                     -- Indique que la trame re�ue est correcte
 
   -- Interfaces du module LAYER2_RX2
   SIGNAL layer2_rx2    : STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Idem que port 1
   SIGNAL layer2_rxval2 : STD_LOGIC;
   SIGNAL layer2_sof2   : STD_LOGIC;
   SIGNAL layer2_eof2   : STD_LOGIC;
   SIGNAL layer2_l2ok2  : STD_LOGIC;
 
   -- Interfaces du module LAYER2_TX
   SIGNAL layer2_txdat     : STD_LOGIC_VECTOR(7 DOWNTO 0);-- Flux de donn�e stuff� + CRC transport
   SIGNAL layer2_txval     : STD_LOGIC;                  -- Indique un octet valide sur layer2_txdat
   SIGNAL layer2_progfull1 : STD_LOGIC;                  -- La FIFO de donn�es Tx port 1 est presque pleine
   SIGNAL layer2_progfull2 : STD_LOGIC;                  -- La FIFO de donn�es Tx port 2 est presque pleine
   SIGNAL layer2_full1     : STD_LOGIC;                  -- La FIFO de donn�es Tx port 1 est pleine
   SIGNAL layer2_full2     : STD_LOGIC;                  -- La FIFO de donn�es Tx port 2 est pleine
 
   -- Signaux de multiplexage des �critures des trames Tx par les 2 PIC
   SIGNAL tx_dat       : STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Flux de donn�es applicatives � transmettre
   SIGNAL val_txdat    : STD_LOGIC;         -- Indique un octet dispo sur tx_dat
   SIGNAL tx_sof       : STD_LOGIC;         -- Indique un d�but de trame
   SIGNAL tx_eof       : STD_LOGIC;         -- Indique une fin de trame
   SIGNAL clr_fifo_tx  : STD_LOGIC;         -- Clear de la FIFO transport Tx
 
 
        COMPONENT autobaud
        PORT(
                clk_sys     : IN STD_LOGIC;
                rst_n       : IN STD_LOGIC;
                rx1         : IN STD_LOGIC;
                val_rx1     : IN STD_LOGIC;
                eof1        : IN STD_LOGIC;
                dat_rx1     : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
      l2_ok1      : IN STD_LOGIC;
                rx2         : IN STD_LOGIC;
                val_rx2     : IN STD_LOGIC;
                eof2        : IN STD_LOGIC;
                dat_rx2     : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
      l2_ok2      : IN STD_LOGIC;
                tc_divclk   : OUT STD_LOGIC_VECTOR(10 downto 0);
                baud_locked : OUT STD_LOGIC
                );
        END COMPONENT;
 
        COMPONENT switch
   GENERIC (
      nbbit_div : INTEGER := 10);
        PORT(
                clk_sys     : IN STD_LOGIC;
                rst_n       : IN STD_LOGIC;
      baud_lock   : IN  STD_LOGIC;
                tc_divclk   : IN STD_LOGIC_VECTOR(nbbit_div-1 downto 0);
                rx          : IN STD_LOGIC;
                rx_dat      : OUT STD_LOGIC_VECTOR(7 downto 0);
                rx_val      : OUT STD_LOGIC;
                tx          : OUT STD_LOGIC;
                tx_dat      : IN STD_LOGIC_VECTOR(7 downto 0);
                tx_rd       : OUT STD_LOGIC;
                tx_empty    : IN STD_LOGIC;
                sw_ena      : IN STD_LOGIC;
                copy_ena    : IN STD_LOGIC;
      etat                 : OUT  STD_LOGIC
                );
        END COMPONENT;
 
        COMPONENT layer2_rx
   GENERIC (
      nbbit_div : INTEGER := 10);
        PORT(
                clk_sys     : IN STD_LOGIC;
                rst_n       : IN STD_LOGIC;
                tc_divclk   : IN STD_LOGIC_VECTOR(nbbit_div-1 downto 0);
                ad_mio      : IN STD_LOGIC_VECTOR(7 downto 0);
                dat_in      : IN STD_LOGIC_VECTOR(7 downto 0);
                val_in      : IN STD_LOGIC;
                dat_out     : OUT STD_LOGIC_VECTOR(7 downto 0);
                val_out     : OUT STD_LOGIC;
                sw_ena      : OUT STD_LOGIC;
                sof         : OUT STD_LOGIC;
                eof         : OUT STD_LOGIC;
                l2_ok       : OUT STD_LOGIC
                );
        END COMPONENT;
 
        COMPONENT frame_store
        PORT(
                clk_sys     : IN STD_LOGIC;
                rst_n       : IN STD_LOGIC;
                dat_in      : IN STD_LOGIC_VECTOR(7 downto 0);
                val_in      : IN STD_LOGIC;
                sof         : IN STD_LOGIC;
                eof         : IN STD_LOGIC;
                l2_ok       : IN STD_LOGIC;
                dat_out     : OUT STD_LOGIC_VECTOR(7 downto 0);
      soc_out     : OUT STD_LOGIC;
                rd_datout   : IN STD_LOGIC;
                new_frame   : OUT STD_LOGIC;
                com_dispo   : OUT STD_LOGIC;
                l7_ok       : OUT STD_LOGIC;
      overflow    : OUT STD_LOGIC
                );
        END COMPONENT;
 
   COMPONENT layer2_tx
   PORT(
      clk_sys     : IN STD_LOGIC;
      rst_n       : IN STD_LOGIC;
      dat_in      : IN STD_LOGIC_VECTOR(7 downto 0);
      val_in      : IN STD_LOGIC;
      sof         : IN STD_LOGIC;
      eof         : IN STD_LOGIC;
      datin_free  : OUT STD_LOGIC;
      dat_out     : OUT STD_LOGIC_VECTOR(7 downto 0);
      val_out     : OUT STD_LOGIC;
      clr_fifo    : IN   STD_LOGIC;
      progfull1   : IN   STD_LOGIC;
      progfull2   : IN   STD_LOGIC;
      full1       : IN   STD_LOGIC;
      empty1      : IN   STD_LOGIC;
      full2       : IN   STD_LOGIC;
      empty2      : IN   STD_LOGIC
      );
   END COMPONENT;
 
   -- La FIFO contient 512 mots, le prog_full est configur� � 500 mots pour laisser une marge de 
   -- stockage avant overflow (voir le module layer2_tx)
   COMPONENT fifo_tx
   PORT (
      clk      : IN STD_LOGIC;
      srst     : IN STD_LOGIC;
      din      : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
      wr_en    : IN STD_LOGIC;
      rd_en    : IN STD_LOGIC;
      dout     : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
      full     : OUT STD_LOGIC;
      empty    : OUT STD_LOGIC;
      prog_full: OUT STD_LOGIC
      );
   END COMPONENT;
 
BEGIN
   --------------------------------------------
   -- Gestion de la m�tastbilit� de rx1 et rx2
   --------------------------------------------
   meta : PROCESS(clk_sys, rst_n)
   BEGIN
      IF (rst_n = '0') THEN
         rx1_r1 <= '1';
         rx1_r2 <= '1';
         rx2_r1 <= '1';
         rx2_r2 <= '1';
      ELSIF (clk_sys'EVENT and clk_sys = '1') THEN
         rx1_r1 <= rx1;
         rx1_r2 <= rx1_r1;
         rx2_r1 <= rx2;
         rx2_r2 <= rx2_r1;
      END IF;
   END PROCESS;
 
        inst_autobaud: autobaud
   PORT MAP(
                clk_sys =>  clk_sys,
                rst_n =>    rst_n,
                rx1 =>      rx1_r2,
                rx2 =>      rx2_r2,
                val_rx1 =>  layer1_val1,
                dat_rx1 =>  layer1_rx1,
      eof1 =>     layer2_eof1,
                l2_ok1 =>   layer2_l2ok1,
                val_rx2 =>  layer1_val2,
      dat_rx2 =>  layer1_rx2,
                eof2 =>     layer2_eof2,
                l2_ok2 =>   layer2_l2ok2,
                tc_divclk => tc_divclk,
                baud_locked => baud_locked
        );
 
        inst_switch1: switch
   GENERIC MAP (
      nbbit_div => nbbit_div)
   PORT MAP(
                clk_sys =>     clk_sys,
                rst_n =>       rst_n,
      baud_lock =>   baud_locked,
                tc_divclk =>   tc_divclk,
                rx =>          rx1_r2,
                rx_dat =>      layer1_rx1,
                rx_val =>      layer1_val1,
                tx =>          tx2,
                tx_dat =>      layer1_tx2,
                tx_rd =>       layer1_rd2,
                tx_empty =>    layer1_empty2,
                sw_ena =>      sw_ena1,
                copy_ena =>    copy_ena1,
      etat =>        OPEN
        );
 
        inst_switch2: switch
   GENERIC MAP (
      nbbit_div => nbbit_div)
   PORT MAP(
                clk_sys =>     clk_sys,
                rst_n =>       rst_n,
      baud_lock =>   baud_locked,
                tc_divclk =>   tc_divclk,
                rx =>          rx2_r2,
                rx_dat =>      layer1_rx2,
                rx_val =>      layer1_val2,
                tx =>          tx1,
                tx_dat =>      layer1_tx1,
                tx_rd =>       layer1_rd1,
                tx_empty =>    layer1_empty1,
                sw_ena =>      sw_ena2,
                copy_ena =>    copy_ena2,
      etat =>        OPEN
        );
 
        inst_layer2_rx1: layer2_rx
   GENERIC MAP (
      nbbit_div => nbbit_div)
   PORT MAP(
                clk_sys =>     clk_sys,
                rst_n =>       rst_n,
                tc_divclk =>   tc_divclk,
      ad_mio =>      ad_mio,
                dat_in =>      layer1_rx1,
                val_in =>      layer1_val1,
                dat_out =>     layer2_rx1,
                val_out =>     layer2_rxval1,
                sof =>         layer2_sof1,
                eof =>         layer2_eof1,
                l2_ok =>       layer2_l2ok1,
                sw_ena =>      sw_ena1
        );
   activity1 <= layer2_eof1;
 
        inst_layer2_rx2: layer2_rx
   GENERIC MAP (
      nbbit_div => nbbit_div)
   PORT MAP(
                clk_sys =>     clk_sys,
                rst_n =>       rst_n,
                tc_divclk =>   tc_divclk,
      ad_mio =>      ad_mio,
                dat_in =>      layer1_rx2,
                val_in =>      layer1_val2,
                dat_out =>     layer2_rx2,
                val_out =>     layer2_rxval2,
                sof =>         layer2_sof2,
                eof =>         layer2_eof2,
                l2_ok =>       layer2_l2ok2,
                sw_ena =>      sw_ena2
        );
   activity2 <= layer2_eof2;
 
        inst_frame_store1_uc1: frame_store
   PORT MAP(
                clk_sys =>     clk_sys,
                rst_n =>       rst_n,
                dat_in =>      layer2_rx1,
                val_in =>      layer2_rxval1,
                sof =>         layer2_sof1,
                eof =>         layer2_eof1,
                l2_ok =>       layer2_l2ok1,
                dat_out =>     layer7_rx1_uc1,
      soc_out =>     layer7_soc1_uc1,
                rd_datout =>   layer7_rd1_uc1,
                new_frame =>   layer7_newframe1_uc1,
                com_dispo =>   layer7_comdispo1_uc1,
                l7_ok =>       layer7_l2ok1_uc1,
      overflow =>    layer7_overflow1_uc1
        );
 
        inst_frame_store1_uc2: frame_store
   PORT MAP(
                clk_sys =>     clk_sys,
                rst_n =>       rst_n,
                dat_in =>      layer2_rx1,
                val_in =>      layer2_rxval1,
                sof =>         layer2_sof1,
                eof =>         layer2_eof1,
                l2_ok =>       layer2_l2ok1,
                dat_out =>     layer7_rx1_uc2,
      soc_out =>     layer7_soc1_uc2,
                rd_datout =>   layer7_rd1_uc2,
                new_frame =>   layer7_newframe1_uc2,
                com_dispo =>   layer7_comdispo1_uc2,
                l7_ok =>       layer7_l2ok1_uc2,
      overflow =>    layer7_overflow1_uc2
        );
 
        inst_frame_store2_uc1: frame_store
   PORT MAP(
                clk_sys =>     clk_sys,
                rst_n =>       rst_n,
                dat_in =>      layer2_rx2,
                val_in =>      layer2_rxval2,
                sof =>         layer2_sof2,
                eof =>         layer2_eof2,
                l2_ok =>       layer2_l2ok2,
                dat_out =>     layer7_rx2_uc1,
      soc_out =>     layer7_soc2_uc1,
                rd_datout =>   layer7_rd2_uc1,
                new_frame =>   layer7_newframe2_uc1,
                com_dispo =>   layer7_comdispo2_uc1,
                l7_ok =>       layer7_l2ok2_uc1,
      overflow =>    layer7_overflow2_uc1
        );
 
        inst_frame_store2_uc2: frame_store
   PORT MAP(
                clk_sys =>     clk_sys,
                rst_n =>       rst_n,
                dat_in =>      layer2_rx2,
                val_in =>      layer2_rxval2,
                sof =>         layer2_sof2,
                eof =>         layer2_eof2,
                l2_ok =>       layer2_l2ok2,
                dat_out =>     layer7_rx2_uc2,
      soc_out =>     layer7_soc2_uc2,
                rd_datout =>   layer7_rd2_uc2,
                new_frame =>   layer7_newframe2_uc2,
                com_dispo =>   layer7_comdispo2_uc2,
                l7_ok =>       layer7_l2ok2_uc2,
      overflow =>    layer7_overflow2_uc2
        );
 
   tx_dat <= tx_dat_uc1 WHEN (val_txdat_uc1 = '1') ELSE tx_dat_uc2;
   val_txdat <= val_txdat_uc1 OR val_txdat_uc2;
   tx_sof <= tx_sof_uc1 OR tx_sof_uc2;
   tx_eof <= tx_eof_uc1 OR tx_eof_uc2;
   clr_fifo_tx <= clr_fifo_tx_uc1 OR clr_fifo_tx_uc2;
 
   inst_layer2_tx: layer2_tx
   PORT MAP(
      clk_sys => clk_sys,
      rst_n => rst_n,
      dat_in => tx_dat,
      val_in => val_txdat,
      sof => tx_sof,
      eof => tx_eof,
      datin_free => txdat_free,
      dat_out => layer2_txdat,
      val_out => layer2_txval,
      clr_fifo => clr_fifo_tx,
      progfull1 => layer2_progfull1,
      progfull2 => layer2_progfull2,
      full1     => layer2_full1,
      empty1    => layer1_empty1,
      full2     => layer2_full2,
      empty2    => layer1_empty2
        );
 
   inst_fifo_tx1 : fifo_tx
   PORT MAP (
      clk =>   clk_sys,
      srst =>  clr_fifo_tx,
      din =>   layer2_txdat,
      wr_en => layer2_txval,
      rd_en => layer1_rd1,
      dout =>  layer1_tx1,
      full =>  layer2_full1,
      empty => layer1_empty1,
      prog_full => layer2_progfull1
   );
 
   inst_fifo_tx2 : fifo_tx
   PORT MAP (
      clk =>   clk_sys,
      srst =>  clr_fifo_tx,
      din =>   layer2_txdat,
      wr_en => layer2_txval,
      rd_en => layer1_rd2,
      dout =>  layer1_tx2,
      full =>  layer2_full2,
      empty => layer1_empty2,
      prog_full => layer2_progfull2
   );
 
END rtl;
 

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[/] [saturn/] [trunk/] [IPCommunication/] [communication_sil4.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	DavidRAMBA	`--=============================================================================`
2			`-- TITRE : COMMUNICATION_SIL4`
3			`-- DESCRIPTION :`
4			`-- Impl�mente la pile communication des MIO s�curitaire pour un module SIL4`
5			`-- FICHIER : communication_sil4.vhd`
6			`--=============================================================================`
7			`-- CREATION`
8			`-- DATE AUTEUR PROJET REVISION`
9			`-- 10/04/2014 DRA SATURN V1.0`
10			`--=============================================================================`
11
12			`LIBRARY IEEE;`
13			`USE IEEE.STD_LOGIC_1164.ALL;`
14			`USE IEEE.STD_LOGIC_ARITH.ALL;`
15			`USE IEEE.STD_LOGIC_UNSIGNED.ALL;`
16
17			`ENTITY communication_sil4 IS`
18			`PORT (`
19			`-- Ports syst�me`
20			`clk_sys : IN STD_LOGIC; -- Clock syst�me`
21			`rst_n : IN STD_LOGIC; -- Reset g�n�ral syst�me`
22			`ad_mio : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- TID du MIO`
23
24			`-- Interfaces s�ries 1 et 2`
25			`rx1 : IN STD_LOGIC; -- R�ception s�rie port 1`
26			`tx1 : OUT STD_LOGIC; -- Transmission s�rie port 1`
27			`rx2 : IN STD_LOGIC; -- R�ception s�rie port 2`
28			`tx2 : OUT STD_LOGIC; -- Transmission s�rie port 2`
29
30			`copy_ena1 : IN STD_LOGIC; -- Autorise la copy du port 1 sur le port 2`
31			`copy_ena2 : IN STD_LOGIC; -- Autorise la copy du port 2 sur le port 1`
32
33			`-- Interfaces de lecture des trames port 1 c�t� �C1`
34			`layer7_rx1_uc1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Donn�es applicatives re�ues sur port 1`
35			`layer7_soc1_uc1 : OUT STD_LOGIC; -- Indique un d�but de trame`
36			`layer7_rd1_uc1 : IN STD_LOGIC; -- Signal de lecture d'un octet de plus`
37			`layer7_newframe1_uc1 : OUT STD_LOGIC; -- Indique la r�ception d'une nouvelle trame`
38			`layer7_comdispo1_uc1 : OUT STD_LOGIC; -- Indique qu'au moins une trame est dispo en m�moire`
39			`layer7_l2ok1_uc1 : OUT STD_LOGIC; -- Indique que la trame re�ue est conforme`
40			`layer7_overflow1_uc1 : OUT STD_LOGIC; -- Indique un d�bordement de m�moire`
41			`activity1 : OUT STD_LOGIC; -- Indique du trafic sur le port 1`
42			`-- Interfaces de lecture des trames port 2 c�t� �C1`
43			`layer7_rx2_uc1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem port 1`
44			`layer7_soc2_uc1 : OUT STD_LOGIC;`
45			`layer7_rd2_uc1 : IN STD_LOGIC;`
46			`layer7_newframe2_uc1 : OUT STD_LOGIC;`
47			`layer7_comdispo2_uc1 : OUT STD_LOGIC;`
48			`layer7_l2ok2_uc1 : OUT STD_LOGIC;`
49			`layer7_overflow2_uc1 : OUT STD_LOGIC;`
50			`activity2 : OUT STD_LOGIC; -- Indique du trafic sur le port 2`
51			`-- Interfaces de lecture des trames port 1 c�t� �C1`
52			`layer7_rx1_uc2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Donn�es applicatives re�ues sur port 1`
53			`layer7_soc1_uc2 : OUT STD_LOGIC; -- Indique un d�but de trame`
54			`layer7_rd1_uc2 : IN STD_LOGIC; -- Signal de lecture d'un octet de plus`
55			`layer7_newframe1_uc2 : OUT STD_LOGIC; -- Indique la r�ception d'une nouvelle trame`
56			`layer7_comdispo1_uc2 : OUT STD_LOGIC; -- Indique qu'au moins une trame est dispo en m�moire`
57			`layer7_l2ok1_uc2 : OUT STD_LOGIC; -- Indique que la trame re�ue est conforme`
58			`layer7_overflow1_uc2 : OUT STD_LOGIC; -- Indique un d�bordement de m�moire`
59			`-- Interfaces de lecture des trames port 2 c�t� �C1`
60			`layer7_rx2_uc2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem port 1`
61			`layer7_soc2_uc2 : OUT STD_LOGIC;`
62			`layer7_rd2_uc2 : IN STD_LOGIC;`
63			`layer7_newframe2_uc2 : OUT STD_LOGIC;`
64			`layer7_comdispo2_uc2 : OUT STD_LOGIC;`
65			`layer7_l2ok2_uc2 : OUT STD_LOGIC;`
66			`layer7_overflow2_uc2 : OUT STD_LOGIC;`
67			`-- Interface d'�criture des trames c�t� �C1`
68			`txdat_free : OUT STD_LOGIC; -- Indique que le module couche transport Tx est dispo`
69			`tx_dat_uc1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Flux de donn�es applicatives � transmettre`
70			`val_txdat_uc1 : IN STD_LOGIC; -- Indique un octet dispo sur tx_dat`
71			`tx_sof_uc1 : IN STD_LOGIC; -- Indique un d�but de trame`
72			`tx_eof_uc1 : IN STD_LOGIC; -- Indique une fin de trame`
73			`clr_fifo_tx_uc1 : IN STD_LOGIC; -- Clear de la FIFO transport Tx`
74			`-- Interface d'�criture des trames c�t� �C2`
75			`tx_dat_uc2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Flux de donn�es applicatives � transmettre`
76			`val_txdat_uc2 : IN STD_LOGIC; -- Indique un octet dispo sur tx_dat`
77			`tx_sof_uc2 : IN STD_LOGIC; -- Indique un d�but de trame`
78			`tx_eof_uc2 : IN STD_LOGIC; -- Indique une fin de trame`
79			`clr_fifo_tx_uc2 : IN STD_LOGIC -- Clear de la FIFO transport Tx`
80			`);`
81			`END communication_sil4;`
82
83			`ARCHITECTURE rtl of communication_sil4 is`
84			`-- D�finit le nombre de bit n�cessaires pour mesurer la dur�e du bit le plus lent avec l'horloge syst�me`
85			`-- i.e. 1 Bit � 50Kbit/s = 20�s nbbit_div = Log2(96MHz x 20�s)`
86			`CONSTANT nbbit_div : INTEGER := 11;`
87
88			`-- DFF pour la m�tastabilit� de rx1 et rx2`
89			`SIGNAL rx1_r1, rx1_r2 : STD_LOGIC;`
90			`SIGNAL rx2_r1, rx2_r2 : STD_LOGIC;`
91
92			`-- Diviseur d'horloge pour le baud rate`
93			`SIGNAL tc_divclk : STD_LOGIC_VECTOR(nbbit_div - 1 DOWNTO 0); -- Termianl count du diviseur`
94			`SIGNAL baud_locked : STD_LOGIC; -- Indique que l'autobaud est lock�`
95
96			`-- Interfaces du SWITCH1`
97			`SIGNAL layer1_rx1 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Flux de donn�e d�serialis� (Rx)`
98			`SIGNAL layer1_val1 : STD_LOGIC; -- Indique un octet valide sur layer1_rx1`
99			`SIGNAL sw_ena1 : STD_LOGIC; -- Indique qu'on est en r�ception entre 2 trames sur port 1`
100			`SIGNAL layer1_tx1 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Flux de donn�e � s�rialiser (Tx)`
101			`SIGNAL layer1_rd1 : STD_LOGIC; -- Demande un octet de plus � transmettre`
102			`SIGNAL layer1_empty1 : STD_LOGIC; -- Indique qu'aucun octet n'est en attente de serialsiation`
103
104			`-- Interfaces du SWITCH2`
105			`SIGNAL layer1_rx2 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem port 1`
106			`SIGNAL layer1_val2 : STD_LOGIC;`
107			`SIGNAL sw_ena2 : STD_LOGIC;`
108			`SIGNAL layer1_tx2 : STD_LOGIC_VECTOR(7 DOWNTO 0);`
109			`SIGNAL layer1_rd2 : STD_LOGIC;`
110			`SIGNAL layer1_empty2 : STD_LOGIC;`
111
112			`-- Interfaces du module LAYER2_RX1`
113			`SIGNAL layer2_rx1 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Flux de donn�es applicatives destuff�`
114			`SIGNAL layer2_rxval1 : STD_LOGIC; -- Indique un octet valide sur layer2_rx1`
115			`SIGNAL layer2_sof1 : STD_LOGIC; -- Indique un d�but de trame`
116			`SIGNAL layer2_eof1 : STD_LOGIC; -- Indqiue une fin de trame`
117			`SIGNAL layer2_l2ok1 : STD_LOGIC; -- Indique que la trame re�ue est correcte`
118
119			`-- Interfaces du module LAYER2_RX2`
120			`SIGNAL layer2_rx2 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Idem que port 1`
121			`SIGNAL layer2_rxval2 : STD_LOGIC;`
122			`SIGNAL layer2_sof2 : STD_LOGIC;`
123			`SIGNAL layer2_eof2 : STD_LOGIC;`
124			`SIGNAL layer2_l2ok2 : STD_LOGIC;`
125
126			`-- Interfaces du module LAYER2_TX`
127			`SIGNAL layer2_txdat : STD_LOGIC_VECTOR(7 DOWNTO 0);-- Flux de donn�e stuff� + CRC transport`
128			`SIGNAL layer2_txval : STD_LOGIC; -- Indique un octet valide sur layer2_txdat`
129			`SIGNAL layer2_progfull1 : STD_LOGIC; -- La FIFO de donn�es Tx port 1 est presque pleine`
130			`SIGNAL layer2_progfull2 : STD_LOGIC; -- La FIFO de donn�es Tx port 2 est presque pleine`
131			`SIGNAL layer2_full1 : STD_LOGIC; -- La FIFO de donn�es Tx port 1 est pleine`
132			`SIGNAL layer2_full2 : STD_LOGIC; -- La FIFO de donn�es Tx port 2 est pleine`
133
134			`-- Signaux de multiplexage des �critures des trames Tx par les 2 PIC`
135			`SIGNAL tx_dat : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Flux de donn�es applicatives � transmettre`
136			`SIGNAL val_txdat : STD_LOGIC; -- Indique un octet dispo sur tx_dat`
137			`SIGNAL tx_sof : STD_LOGIC; -- Indique un d�but de trame`
138			`SIGNAL tx_eof : STD_LOGIC; -- Indique une fin de trame`
139			`SIGNAL clr_fifo_tx : STD_LOGIC; -- Clear de la FIFO transport Tx`
140
141
142			`COMPONENT autobaud`
143			`PORT(`
144			`clk_sys : IN STD_LOGIC;`
145			`rst_n : IN STD_LOGIC;`
146			`rx1 : IN STD_LOGIC;`
147			`val_rx1 : IN STD_LOGIC;`
148			`eof1 : IN STD_LOGIC;`
149			`dat_rx1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
150			`l2_ok1 : IN STD_LOGIC;`
151			`rx2 : IN STD_LOGIC;`
152			`val_rx2 : IN STD_LOGIC;`
153			`eof2 : IN STD_LOGIC;`
154			`dat_rx2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
155			`l2_ok2 : IN STD_LOGIC;`
156			`tc_divclk : OUT STD_LOGIC_VECTOR(10 downto 0);`
157			`baud_locked : OUT STD_LOGIC`
158			`);`
159			`END COMPONENT;`
160
161			`COMPONENT switch`
162			`GENERIC (`
163			`nbbit_div : INTEGER := 10);`
164			`PORT(`
165			`clk_sys : IN STD_LOGIC;`
166			`rst_n : IN STD_LOGIC;`
167			`baud_lock : IN STD_LOGIC;`
168			`tc_divclk : IN STD_LOGIC_VECTOR(nbbit_div-1 downto 0);`
169			`rx : IN STD_LOGIC;`
170			`rx_dat : OUT STD_LOGIC_VECTOR(7 downto 0);`
171			`rx_val : OUT STD_LOGIC;`
172			`tx : OUT STD_LOGIC;`
173			`tx_dat : IN STD_LOGIC_VECTOR(7 downto 0);`
174			`tx_rd : OUT STD_LOGIC;`
175			`tx_empty : IN STD_LOGIC;`
176			`sw_ena : IN STD_LOGIC;`
177			`copy_ena : IN STD_LOGIC;`
178			`etat : OUT STD_LOGIC`
179			`);`
180			`END COMPONENT;`
181
182			`COMPONENT layer2_rx`
183			`GENERIC (`
184			`nbbit_div : INTEGER := 10);`
185			`PORT(`
186			`clk_sys : IN STD_LOGIC;`
187			`rst_n : IN STD_LOGIC;`
188			`tc_divclk : IN STD_LOGIC_VECTOR(nbbit_div-1 downto 0);`
189			`ad_mio : IN STD_LOGIC_VECTOR(7 downto 0);`
190			`dat_in : IN STD_LOGIC_VECTOR(7 downto 0);`
191			`val_in : IN STD_LOGIC;`
192			`dat_out : OUT STD_LOGIC_VECTOR(7 downto 0);`
193			`val_out : OUT STD_LOGIC;`
194			`sw_ena : OUT STD_LOGIC;`
195			`sof : OUT STD_LOGIC;`
196			`eof : OUT STD_LOGIC;`
197			`l2_ok : OUT STD_LOGIC`
198			`);`
199			`END COMPONENT;`
200
201			`COMPONENT frame_store`
202			`PORT(`
203			`clk_sys : IN STD_LOGIC;`
204			`rst_n : IN STD_LOGIC;`
205			`dat_in : IN STD_LOGIC_VECTOR(7 downto 0);`
206			`val_in : IN STD_LOGIC;`
207			`sof : IN STD_LOGIC;`
208			`eof : IN STD_LOGIC;`
209			`l2_ok : IN STD_LOGIC;`
210			`dat_out : OUT STD_LOGIC_VECTOR(7 downto 0);`
211			`soc_out : OUT STD_LOGIC;`
212			`rd_datout : IN STD_LOGIC;`
213			`new_frame : OUT STD_LOGIC;`
214			`com_dispo : OUT STD_LOGIC;`
215			`l7_ok : OUT STD_LOGIC;`
216			`overflow : OUT STD_LOGIC`
217			`);`
218			`END COMPONENT;`
219
220			`COMPONENT layer2_tx`
221			`PORT(`
222			`clk_sys : IN STD_LOGIC;`
223			`rst_n : IN STD_LOGIC;`
224			`dat_in : IN STD_LOGIC_VECTOR(7 downto 0);`
225			`val_in : IN STD_LOGIC;`
226			`sof : IN STD_LOGIC;`
227			`eof : IN STD_LOGIC;`
228			`datin_free : OUT STD_LOGIC;`
229			`dat_out : OUT STD_LOGIC_VECTOR(7 downto 0);`
230			`val_out : OUT STD_LOGIC;`
231			`clr_fifo : IN STD_LOGIC;`
232			`progfull1 : IN STD_LOGIC;`
233			`progfull2 : IN STD_LOGIC;`
234			`full1 : IN STD_LOGIC;`
235			`empty1 : IN STD_LOGIC;`
236			`full2 : IN STD_LOGIC;`
237			`empty2 : IN STD_LOGIC`
238			`);`
239			`END COMPONENT;`
240
241			`-- La FIFO contient 512 mots, le prog_full est configur� � 500 mots pour laisser une marge de`
242			`-- stockage avant overflow (voir le module layer2_tx)`
243			`COMPONENT fifo_tx`
244			`PORT (`
245			`clk : IN STD_LOGIC;`
246			`srst : IN STD_LOGIC;`
247			`din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
248			`wr_en : IN STD_LOGIC;`
249			`rd_en : IN STD_LOGIC;`
250			`dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);`
251			`full : OUT STD_LOGIC;`
252			`empty : OUT STD_LOGIC;`
253			`prog_full: OUT STD_LOGIC`
254			`);`
255			`END COMPONENT;`
256
257			`BEGIN`
258			`--------------------------------------------`
259			`-- Gestion de la m�tastbilit� de rx1 et rx2`
260			`--------------------------------------------`
261			`meta : PROCESS(clk_sys, rst_n)`
262			`BEGIN`
263			`IF (rst_n = '0') THEN`
264			`rx1_r1 <= '1';`
265			`rx1_r2 <= '1';`
266			`rx2_r1 <= '1';`
267			`rx2_r2 <= '1';`
268			`ELSIF (clk_sys'EVENT and clk_sys = '1') THEN`
269			`rx1_r1 <= rx1;`
270			`rx1_r2 <= rx1_r1;`
271			`rx2_r1 <= rx2;`
272			`rx2_r2 <= rx2_r1;`
273			`END IF;`
274			`END PROCESS;`
275
276			`inst_autobaud: autobaud`
277			`PORT MAP(`
278			`clk_sys => clk_sys,`
279			`rst_n => rst_n,`
280			`rx1 => rx1_r2,`
281			`rx2 => rx2_r2,`
282			`val_rx1 => layer1_val1,`
283			`dat_rx1 => layer1_rx1,`
284			`eof1 => layer2_eof1,`
285			`l2_ok1 => layer2_l2ok1,`
286			`val_rx2 => layer1_val2,`
287			`dat_rx2 => layer1_rx2,`
288			`eof2 => layer2_eof2,`
289			`l2_ok2 => layer2_l2ok2,`
290			`tc_divclk => tc_divclk,`
291			`baud_locked => baud_locked`
292			`);`
293
294			`inst_switch1: switch`
295			`GENERIC MAP (`
296			`nbbit_div => nbbit_div)`
297			`PORT MAP(`
298			`clk_sys => clk_sys,`
299			`rst_n => rst_n,`
300			`baud_lock => baud_locked,`
301			`tc_divclk => tc_divclk,`
302			`rx => rx1_r2,`
303			`rx_dat => layer1_rx1,`
304			`rx_val => layer1_val1,`
305			`tx => tx2,`
306			`tx_dat => layer1_tx2,`
307			`tx_rd => layer1_rd2,`
308			`tx_empty => layer1_empty2,`
309			`sw_ena => sw_ena1,`
310			`copy_ena => copy_ena1,`
311			`etat => OPEN`
312			`);`
313
314			`inst_switch2: switch`
315			`GENERIC MAP (`
316			`nbbit_div => nbbit_div)`
317			`PORT MAP(`
318			`clk_sys => clk_sys,`
319			`rst_n => rst_n,`
320			`baud_lock => baud_locked,`
321			`tc_divclk => tc_divclk,`
322			`rx => rx2_r2,`
323			`rx_dat => layer1_rx2,`
324			`rx_val => layer1_val2,`
325			`tx => tx1,`
326			`tx_dat => layer1_tx1,`
327			`tx_rd => layer1_rd1,`
328			`tx_empty => layer1_empty1,`
329			`sw_ena => sw_ena2,`
330			`copy_ena => copy_ena2,`
331			`etat => OPEN`
332			`);`
333
334			`inst_layer2_rx1: layer2_rx`
335			`GENERIC MAP (`
336			`nbbit_div => nbbit_div)`
337			`PORT MAP(`
338			`clk_sys => clk_sys,`
339			`rst_n => rst_n,`
340			`tc_divclk => tc_divclk,`
341			`ad_mio => ad_mio,`
342			`dat_in => layer1_rx1,`
343			`val_in => layer1_val1,`
344			`dat_out => layer2_rx1,`
345			`val_out => layer2_rxval1,`
346			`sof => layer2_sof1,`
347			`eof => layer2_eof1,`
348			`l2_ok => layer2_l2ok1,`
349			`sw_ena => sw_ena1`
350			`);`
351			`activity1 <= layer2_eof1;`
352
353			`inst_layer2_rx2: layer2_rx`
354			`GENERIC MAP (`
355			`nbbit_div => nbbit_div)`
356			`PORT MAP(`
357			`clk_sys => clk_sys,`
358			`rst_n => rst_n,`
359			`tc_divclk => tc_divclk,`
360			`ad_mio => ad_mio,`
361			`dat_in => layer1_rx2,`
362			`val_in => layer1_val2,`
363			`dat_out => layer2_rx2,`
364			`val_out => layer2_rxval2,`
365			`sof => layer2_sof2,`
366			`eof => layer2_eof2,`
367			`l2_ok => layer2_l2ok2,`
368			`sw_ena => sw_ena2`
369			`);`
370			`activity2 <= layer2_eof2;`
371
372			`inst_frame_store1_uc1: frame_store`
373			`PORT MAP(`
374			`clk_sys => clk_sys,`
375			`rst_n => rst_n,`
376			`dat_in => layer2_rx1,`
377			`val_in => layer2_rxval1,`
378			`sof => layer2_sof1,`
379			`eof => layer2_eof1,`
380			`l2_ok => layer2_l2ok1,`
381			`dat_out => layer7_rx1_uc1,`
382			`soc_out => layer7_soc1_uc1,`
383			`rd_datout => layer7_rd1_uc1,`
384			`new_frame => layer7_newframe1_uc1,`
385			`com_dispo => layer7_comdispo1_uc1,`
386			`l7_ok => layer7_l2ok1_uc1,`
387			`overflow => layer7_overflow1_uc1`
388			`);`
389
390			`inst_frame_store1_uc2: frame_store`
391			`PORT MAP(`
392			`clk_sys => clk_sys,`
393			`rst_n => rst_n,`
394			`dat_in => layer2_rx1,`
395			`val_in => layer2_rxval1,`
396			`sof => layer2_sof1,`
397			`eof => layer2_eof1,`
398			`l2_ok => layer2_l2ok1,`
399			`dat_out => layer7_rx1_uc2,`
400			`soc_out => layer7_soc1_uc2,`
401			`rd_datout => layer7_rd1_uc2,`
402			`new_frame => layer7_newframe1_uc2,`
403			`com_dispo => layer7_comdispo1_uc2,`
404			`l7_ok => layer7_l2ok1_uc2,`
405			`overflow => layer7_overflow1_uc2`
406			`);`
407
408			`inst_frame_store2_uc1: frame_store`
409			`PORT MAP(`
410			`clk_sys => clk_sys,`
411			`rst_n => rst_n,`
412			`dat_in => layer2_rx2,`
413			`val_in => layer2_rxval2,`
414			`sof => layer2_sof2,`
415			`eof => layer2_eof2,`
416			`l2_ok => layer2_l2ok2,`
417			`dat_out => layer7_rx2_uc1,`
418			`soc_out => layer7_soc2_uc1,`
419			`rd_datout => layer7_rd2_uc1,`
420			`new_frame => layer7_newframe2_uc1,`
421			`com_dispo => layer7_comdispo2_uc1,`
422			`l7_ok => layer7_l2ok2_uc1,`
423			`overflow => layer7_overflow2_uc1`
424			`);`
425
426			`inst_frame_store2_uc2: frame_store`
427			`PORT MAP(`
428			`clk_sys => clk_sys,`
429			`rst_n => rst_n,`
430			`dat_in => layer2_rx2,`
431			`val_in => layer2_rxval2,`
432			`sof => layer2_sof2,`
433			`eof => layer2_eof2,`
434			`l2_ok => layer2_l2ok2,`
435			`dat_out => layer7_rx2_uc2,`
436			`soc_out => layer7_soc2_uc2,`
437			`rd_datout => layer7_rd2_uc2,`
438			`new_frame => layer7_newframe2_uc2,`
439			`com_dispo => layer7_comdispo2_uc2,`
440			`l7_ok => layer7_l2ok2_uc2,`
441			`overflow => layer7_overflow2_uc2`
442			`);`
443
444			`tx_dat <= tx_dat_uc1 WHEN (val_txdat_uc1 = '1') ELSE tx_dat_uc2;`
445			`val_txdat <= val_txdat_uc1 OR val_txdat_uc2;`
446			`tx_sof <= tx_sof_uc1 OR tx_sof_uc2;`
447			`tx_eof <= tx_eof_uc1 OR tx_eof_uc2;`
448			`clr_fifo_tx <= clr_fifo_tx_uc1 OR clr_fifo_tx_uc2;`
449
450			`inst_layer2_tx: layer2_tx`
451			`PORT MAP(`
452			`clk_sys => clk_sys,`
453			`rst_n => rst_n,`
454			`dat_in => tx_dat,`
455			`val_in => val_txdat,`
456			`sof => tx_sof,`
457			`eof => tx_eof,`
458			`datin_free => txdat_free,`
459			`dat_out => layer2_txdat,`
460			`val_out => layer2_txval,`
461			`clr_fifo => clr_fifo_tx,`
462			`progfull1 => layer2_progfull1,`
463			`progfull2 => layer2_progfull2,`
464			`full1 => layer2_full1,`
465			`empty1 => layer1_empty1,`
466			`full2 => layer2_full2,`
467			`empty2 => layer1_empty2`
468			`);`
469
470			`inst_fifo_tx1 : fifo_tx`
471			`PORT MAP (`
472			`clk => clk_sys,`
473			`srst => clr_fifo_tx,`
474			`din => layer2_txdat,`
475			`wr_en => layer2_txval,`
476			`rd_en => layer1_rd1,`
477			`dout => layer1_tx1,`
478			`full => layer2_full1,`
479			`empty => layer1_empty1,`
480			`prog_full => layer2_progfull1`
481			`);`
482
483			`inst_fifo_tx2 : fifo_tx`
484			`PORT MAP (`
485			`clk => clk_sys,`
486			`srst => clr_fifo_tx,`
487			`din => layer2_txdat,`
488			`wr_en => layer2_txval,`
489			`rd_en => layer1_rd2,`
490			`dout => layer1_tx2,`
491			`full => layer2_full2,`
492			`empty => layer1_empty2,`
493			`prog_full => layer2_progfull2`
494			`);`
495
496			`END rtl;`
497