OpenCores
URL https://opencores.org/ocsvn/sc2v/sc2v/trunk

Subversion Repositories sc2v

[/] [sc2v/] [tags/] [arelease/] [README] - Blame information for rev 36

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 jcastillo
/*
2
 *  This program is free software; you can redistribute it and/or modify
3
 *  it under the terms of the GNU General Public License as published by
4
 *  the Free Software Foundation; either version 2 of the License, or
5
 *  (at your option) any later version.
6
 *
7
 *  This program is distributed in the hope that it will be useful,
8
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
9
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10
 *  GNU Library General Public License for more details.
11
 *
12
 *  You should have received a copy of the GNU General Public License
13
 *  along with this program; if not, write to the Free Software
14
 *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
15
 */
16
 
17
  Authors:
18
 
19
            Pablo Huerta (phuerta@opensocdesign.com)
20
            Javier Castillo (jcastillo@opensocdesign.com)
21
 
22
  Contributors:
23
 
24
             David Moloney
25
 
26
 
27
 
28
INSTRUCTIONS OF USE:
29
 
30
1- Compiling the sources:
31
 
32
The sc2v translator is based on lex and yacc tools. You need lex and yacc
33
installed before trying to compile sc2v.
34
 
35
For compiling the sources just type "make" under the directory you unzipped the
36
fonts. It will generate two executables: sc2v_step1 and sc2v_step2.
37
 
38
 
39
2- Translating an SystemC module:
40
 
41
The translation is done in two steps. First you must translate the .cpp file by
42
typing: sc2v_step1 < file.cpp
43
Second step consists in traslating the .h file: sc2v_step2 < file.h > file.v
44
 
45
3- Format and restrictions of the SystemC files:
46
 
47
        - Each module must have a .h file with the declarations of ports,
48
        signals, and processes, and there must exist a .cpp file with the code
49
        of the processes.
50
 
51
        - For writing to a port or a signal you must ALWAYS use the .write()
52
        method.
53
 
54
        - You cannot use functions.
55
 
56
        -Macros with no parameters are supported, but may cause little problems
57
        with name of variables. Macros with parameters are not supported.
58
 
59
        -Only data types: bool, sc_int, sc_bigint, sc_uint and sc_biguint are
60
        supported.
61
 
62
        -No enumerated types supported.
63
 
64
        -No global variables supported.
65
 
66
4- Known bugs
67
 
68
        -Concatenation is not yet supported. If you use concatenations like:
69
        (var1, var2), in the verilog file will appear identically, so you must
70
        replace the "(" and ")" by "{" and "}" manually.
71
 
72
        -The usage of macros and defines may cause some errors.
73
 
74
        -Using comments in switch case structures may cause errors. Specially
75
        when using structures like:
76
 
77
                case 1: //Comment here
78
                case 2:
79
                //Or comment here
80
                case 3:
81
 
82
        Better write it like this:
83
 
84
                //Comment for 1, 2 and 3
85
                case 1:
86
                case 2:
87
                case 3:
88
                        instructions . . .
89
                        instructions . . .
90
                        instructions . . .
91
 
92
        A general rule would be: "Don't use comments in the same line of case or
93
        in the inmediate next line. Use comments in the line before the case
94
        statement"
95
 
96
5- For testing the application we recommend to use the systemcdes or the
97
systemcmd5 cores, both available at www.opencores.org.
98
 
99
6- For any doubt, comment, or for reporting bugs, feel free to write to
100
sc2v@opensocdesign.com
101
 
102
 
103
TODO:
104
 
105
        - Repair all known bugs.
106
        - Make functions supported.
107
        - Make macros fully supported.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.