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[/] [sc2v/] [trunk/] [src/] [sc2v_step1.h] - Blame information for rev 16

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Line No. Rev Author Line
1 14 jcastillo
/* -----------------------------------------------------------------------------
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 *
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 *  SystemC to Verilog Translator v0.4
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 *  Provided by OpenSoc Design
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 *
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 *  www.opensocdesign.com
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 *
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 * -----------------------------------------------------------------------------
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 *  This program is free software; you can redistribute it and/or modify
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 *  it under the terms of the GNU General Public License as published by
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 *  the Free Software Foundation; either version 2 of the License, or
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 *  (at your option) any later version.
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 *
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 *  This program is distributed in the hope that it will be useful,
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 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 *  GNU Library General Public License for more details.
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 *
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 *  You should have received a copy of the GNU General Public License
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 *  along with this program; if not, write to the Free Software
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 *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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 */
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#include "sglib.h"
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#define MAX_NAME_LENGTH 256
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typedef struct _DefineNode
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{
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  char name[MAX_NAME_LENGTH];
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  struct _DefineNode *next;
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} DefineNode;
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typedef struct _RegNode
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{
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  char name[MAX_NAME_LENGTH];
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  char name2[MAX_NAME_LENGTH];
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  struct _RegNode *next;
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} RegNode;
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/* Global var to store Regs */
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  RegNode *regslist;
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/* Global var to store Defines */
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  DefineNode *defineslist;
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/* Functions for defines list*/
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DefineNode *InsertDefine(DefineNode *list,char *name);
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int IsDefine(DefineNode *list,char *name);
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/* Functions for registers list*/
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RegNode *InsertReg(RegNode *list, char *name, char *name2);
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char *IsReg (RegNode *list,char *name);
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