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[/] [sc2v/] [trunk/] [src/] [sc2v_step3.l] - Blame information for rev 36

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1 4 jcastillo
/* -----------------------------------------------------------------------------
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 *
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 *  SystemC to Verilog Translator v0.4
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 *  Provided by Universidad Rey Juan Carlos
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 *
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 * -----------------------------------------------------------------------------
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 *  This program is free software; you can redistribute it and/or modify
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 *  it under the terms of the GNU General Public License as published by
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 *  the Free Software Foundation; either version 2 of the License, or
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 *  (at your option) any later version.
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 *
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 *  This program is distributed in the hope that it will be useful,
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 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 *  GNU Library General Public License for more details.
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 *
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 *  You should have received a copy of the GNU General Public License
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 *  along with this program; if not, write to the Free Software
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 *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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 */
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%{
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#include 
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#include "y.tab.h"
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extern int yylval;
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%}
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%%
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"module"[" "]*[a-zA-Z][_a-zA-Z0-9]*[" "]*["("] yylval=(int)strdup(yytext); return MODULE;
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"("[" "]*[a-zA-Z][_a-zA-Z0-9" "\[\]:]*[,][ ]*  yylval=(int)strdup(yytext); return WORDCOLON;
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[" "]*[a-zA-Z][_a-zA-Z0-9" "\[\]:]*            yylval=(int)strdup(yytext); return WORD;
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"("[ ]*                                        return OPENPAR;
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[ ]*")"                                        return CLOSEPAR;
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[.:"^"!%=/+*_"&""-"<>"?""|""\\"][ ]*           yylval=(int)strdup(yytext); return SYMBOL;
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%%

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