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Subversion Repositories scan_based_serial_communication

[/] [scan_based_serial_communication/] [trunk/] [scan.perl.v] - Blame information for rev 4

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////////////////////////////////////////////////////////////////////////////////
 
module scan (
 
              // Inputs & outputs to the chip
             PERL begin
             /*
              DEPERLIFY_INCLUDE(scan_signal_list.pl);
 
              for (my $i = 0; $i < scalar @signal_list; $i++) {
                 print "              $signal_list[$i]{name},\n";
              }
 
              */
             end
 
              // To the pads
              scan_phi,
              scan_phi_bar,
              scan_data_in,
              scan_data_out,
              scan_load_chip,
              scan_load_chain
 
              );
 
 
   // /////////////////////////////////////////////////////////////////////
   // Ports
 
   // Scans
   input   scan_phi;
   input   scan_phi_bar;
   input   scan_data_in;
   output  scan_data_out;
   input   scan_load_chain;
   input   scan_load_chip;
 
 
   PERL begin
      /*
       DEPERLIFY_INCLUDE(scan_signal_list.pl);
 
       for (my $i = 0; $i < scalar @signal_list; $i++) {
           if ($signal_list[$i]{writable} == 1) {
                print "   output reg ";
           } else {
                print "   input      ";
           }
 
            print "[$signal_list[$i]{size}-1:0]  $signal_list[$i]{name};\n";
       }
 
       */
   end
 
 
   // /////////////////////////////////////////////////////////////////////
   // Implementation
 
   // The scan chain is comprised of two sets of latches: scan_master and scan_slave.
 
   PERL begin
      /*
 
       ##############################################################
       # Modify scan_signal_list.pl in order to change the signals. #
       ##############################################################
 
       DEPERLIFY_INCLUDE(scan_signal_list.pl);
 
       # Print scan chain latches
       print "   reg [$scan_chain_length-1:0] scan_master;\n";
       print "   reg [$scan_chain_length-1:0] scan_slave;\n\n";
 
       # Print scan_load and scan_next logic
       print "   reg  [$scan_chain_length-1:0] scan_load;\n";
       print "   wire [$scan_chain_length-1:0] scan_next;\n\n";
 
       print "   always @ (*) begin\n";
 
       for (my $i = 0; $i < scalar @signal_list; $i++) {
 
          my $name      = $signal_list[$i]{name};
          my $size      = $signal_list[$i]{size};
          my $addr_bits = $signal_list[$i]{addr_bits};
          my $data_bits = $signal_list[$i]{data_bits};
 
          my $size_begin = $signal_list[$i]{start};
          my $size_end   = $size_begin + $size - 1;
 
          my $addr_begin = $signal_list[$i]{start};
          my $addr_end   = $addr_begin + $addr_bits - 1;
 
          my $data_begin = $addr_end + 1;
          my $data_end   = $data_begin + $data_bits - 1;
 
          if ($signal_list[$i]{addr_bits} == 0) {
             print "      scan_load[$size_end:$size_begin] = ${name};\n";
          } else {
             print "      scan_load[$addr_end:$addr_begin] = scan_slave[$addr_end:$addr_begin];\n";
             print "      case (scan_slave[$addr_end:$addr_begin])\n";
             for (my $a = 0; ($a+1-1)*$data_bits < $size; $a++) {
                print "         ${addr_bits}'d${a}: scan_load[$data_end:$data_begin] = ${name}[$a*$data_bits +: $data_bits];\n";
             }
             print "      endcase\n";
          }
       }
 
       print "   end\n\n";
 
       print "   assign scan_next = scan_load_chain ? scan_load : {scan_data_in, scan_slave[$'$scan_chain_length-1:1]};\n\n";
 
       # Print latches
       print "   //synopsys one_hot \"scan_phi, scan_phi_bar\"\n";
       print "   always @ (*) begin\n";
       print "       if (scan_phi)\n";
       print "          scan_master = scan_next;\n";
       print "       if (scan_phi_bar)\n";
       print "          scan_slave  = scan_master;\n";
       print "   end\n\n";
 
       # Print input latches
       print "   always @ (*) if (scan_load_chip) begin\n";
 
       for (my $i = 0; $i < scalar @signal_list; $i++) {
          if ($signal_list[$i]{writable} == 1) {
 
             my $name      = $signal_list[$i]{name};
             my $size      = $signal_list[$i]{size};
             my $addr_bits = $signal_list[$i]{addr_bits};
             my $data_bits = $signal_list[$i]{data_bits};
 
             my $size_begin = $signal_list[$i]{start};
             my $size_end   = $size_begin + $size - 1;
 
             my $addr_begin = $signal_list[$i]{start};
             my $addr_end   = $addr_begin + $addr_bits - 1;
 
             my $data_begin = $addr_end + 1;
             my $data_end   = $data_begin + $data_bits - 1;
 
             if ($signal_list[$i]{addr_bits} == 0) {
                print "      $name = scan_slave[$size_end:$size_begin];\n";
             } else {
                if ($scan_reset_exists) {
                   print "      if (scan_slave[$scan_reset_bit]) ${name} = ${size}'d0; else\n";
                }
                print "      case (scan_slave[$addr_end:$addr_begin])\n";
                for (my $a = 0; ($a+1-1)*$data_bits < $size; $a++) {
                   print "         ${addr_bits}'d${a}: ${name}[$a*$data_bits +: $data_bits] = scan_slave[$data_end:$data_begin];\n";
                }
                print "      endcase\n";
             }
          }
       }
 
       print "   end\n\n";
 
       # Print data_out
       print "   assign scan_data_out = scan_slave[0];\n";
 
       */
   end
 
 
   // /////////////////////////////////////////////////////////////////////
 
endmodule

Line No.	Rev	Author	Line
1	3	Quanticles
2
3			`////////////////////////////////////////////////////////////////////////////////`
4
5			`module scan (`
6
7			`// Inputs & outputs to the chip`
8			`PERL begin`
9			`/*`
10			`DEPERLIFY_INCLUDE(scan_signal_list.pl);`
11
12			`for (my $i = 0; $i < scalar @signal_list; $i++) {`
13			`print " $signal_list[$i]{name},\n";`
14			`}`
15
16			`*/`
17			`end`
18
19			`// To the pads`
20			`scan_phi,`
21			`scan_phi_bar,`
22			`scan_data_in,`
23			`scan_data_out,`
24			`scan_load_chip,`
25			`scan_load_chain`
26
27			`);`
28
29
30			`// /////////////////////////////////////////////////////////////////////`
31			`// Ports`
32
33			`// Scans`
34			`input scan_phi;`
35			`input scan_phi_bar;`
36			`input scan_data_in;`
37			`output scan_data_out;`
38			`input scan_load_chain;`
39			`input scan_load_chip;`
40
41
42			`PERL begin`
43			`/*`
44			`DEPERLIFY_INCLUDE(scan_signal_list.pl);`
45
46			`for (my $i = 0; $i < scalar @signal_list; $i++) {`
47			`if ($signal_list[$i]{writable} == 1) {`
48	4	Quanticles	`print " output reg ";`
49	3	Quanticles	`} else {`
50	4	Quanticles	`print " input ";`
51	3	Quanticles	`}`
52
53			`print "[$signal_list[$i]{size}-1:0] $signal_list[$i]{name};\n";`
54			`}`
55
56			`*/`
57			`end`
58
59
60			`// /////////////////////////////////////////////////////////////////////`
61			`// Implementation`
62
63			`// The scan chain is comprised of two sets of latches: scan_master and scan_slave.`
64
65			`PERL begin`
66			`/*`
67
68			`##############################################################`
69			`# Modify scan_signal_list.pl in order to change the signals. #`
70			`##############################################################`
71
72			`DEPERLIFY_INCLUDE(scan_signal_list.pl);`
73
74			`# Print scan chain latches`
75			`print " reg [$scan_chain_length-1:0] scan_master;\n";`
76			`print " reg [$scan_chain_length-1:0] scan_slave;\n\n";`
77
78			`# Print scan_load and scan_next logic`
79	4	Quanticles	`print " reg [$scan_chain_length-1:0] scan_load;\n";`
80	3	Quanticles	`print " wire [$scan_chain_length-1:0] scan_next;\n\n";`
81
82	4	Quanticles	`print " always @ (*) begin\n";`
83
84	3	Quanticles	`for (my $i = 0; $i < scalar @signal_list; $i++) {`
85
86	4	Quanticles	`my $name = $signal_list[$i]{name};`
87			`my $size = $signal_list[$i]{size};`
88			`my $addr_bits = $signal_list[$i]{addr_bits};`
89			`my $data_bits = $signal_list[$i]{data_bits};`
90	3	Quanticles
91	4	Quanticles	`my $size_begin = $signal_list[$i]{start};`
92			`my $size_end = $size_begin + $size - 1;`
93
94			`my $addr_begin = $signal_list[$i]{start};`
95			`my $addr_end = $addr_begin + $addr_bits - 1;`
96
97			`my $data_begin = $addr_end + 1;`
98			`my $data_end = $data_begin + $data_bits - 1;`
99
100			`if ($signal_list[$i]{addr_bits} == 0) {`
101			`print " scan_load[$size_end:$size_begin] = ${name};\n";`
102			`} else {`
103			`print " scan_load[$addr_end:$addr_begin] = scan_slave[$addr_end:$addr_begin];\n";`
104			`print " case (scan_slave[$addr_end:$addr_begin])\n";`
105			`for (my $a = 0; ($a+1-1)*$data_bits < $size; $a++) {`
106			`print " ${addr_bits}'d${a}: scan_load[$data_end:$data_begin] = ${name}[$a*$data_bits +: $data_bits];\n";`
107			`}`
108			`print " endcase\n";`
109			`}`
110	3	Quanticles	`}`
111
112	4	Quanticles	`print " end\n\n";`
113	3	Quanticles
114	4	Quanticles	`print " assign scan_next = scan_load_chain ? scan_load : {scan_data_in, scan_slave[$'$scan_chain_length-1:1]};\n\n";`
115
116	3	Quanticles	`# Print latches`
117			`print " //synopsys one_hot \"scan_phi, scan_phi_bar\"\n";`
118			`print " always @ (*) begin\n";`
119			`print " if (scan_phi)\n";`
120			`print " scan_master = scan_next;\n";`
121			`print " if (scan_phi_bar)\n";`
122			`print " scan_slave = scan_master;\n";`
123			`print " end\n\n";`
124
125			`# Print input latches`
126	4	Quanticles	`print " always @ (*) if (scan_load_chip) begin\n";`
127
128	3	Quanticles	`for (my $i = 0; $i < scalar @signal_list; $i++) {`
129			`if ($signal_list[$i]{writable} == 1) {`
130	4	Quanticles
131			`my $name = $signal_list[$i]{name};`
132			`my $size = $signal_list[$i]{size};`
133			`my $addr_bits = $signal_list[$i]{addr_bits};`
134			`my $data_bits = $signal_list[$i]{data_bits};`
135
136			`my $size_begin = $signal_list[$i]{start};`
137			`my $size_end = $size_begin + $size - 1;`
138
139			`my $addr_begin = $signal_list[$i]{start};`
140			`my $addr_end = $addr_begin + $addr_bits - 1;`
141
142			`my $data_begin = $addr_end + 1;`
143			`my $data_end = $data_begin + $data_bits - 1;`
144
145			`if ($signal_list[$i]{addr_bits} == 0) {`
146			`print " $name = scan_slave[$size_end:$size_begin];\n";`
147			`} else {`
148			`if ($scan_reset_exists) {`
149			`print " if (scan_slave[$scan_reset_bit]) ${name} = ${size}'d0; else\n";`
150			`}`
151			`print " case (scan_slave[$addr_end:$addr_begin])\n";`
152			`for (my $a = 0; ($a+1-1)*$data_bits < $size; $a++) {`
153			`print " ${addr_bits}'d${a}: ${name}[$a*$data_bits +: $data_bits] = scan_slave[$data_end:$data_begin];\n";`
154			`}`
155			`print " endcase\n";`
156			`}`
157	3	Quanticles	`}`
158			`}`
159
160	4	Quanticles	`print " end\n\n";`
161
162	3	Quanticles	`# Print data_out`
163			`print " assign scan_data_out = scan_slave[0];\n";`
164
165			`*/`
166			`end`
167
168
169			`// /////////////////////////////////////////////////////////////////////`
170
171			`endmodule`

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Subversion Repositories scan_based_serial_communication

[/] [scan_based_serial_communication/] [trunk/] [scan.perl.v] - Blame information for rev 4