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[/] [scarm/] [branches/] [release_0_1/] [src/] [scEX.cpp] - Blame information for rev 5

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1 5 zhong 
// scEX.cpp: implementation of the scEX class.
2 
//
3 
//////////////////////////////////////////////////////////////////////
4 
 
5 
#include "scEX.h"
6 
#define DEBUG
7 
 
8 
 
9 
//////////////////////////////////////////////////////////////////////
10 
// Construction/Destruction
11 
//////////////////////////////////////////////////////////////////////
12 
 
13 
scEX::scEX(sc_module_name name_):sc_module(name_)
14 
  ,mult("mutiplier")
15 
  ,bsh("shifter")
16 
  ,alu("alu")
17 
{
18 
        m_last_Rd=REGS(0);
19 
        m_b_last_Load=false;
20 
        m_last_OP=OP_TST;
21 
         m_is_Rs=false;
22 
         m_is_Rm=false;
23 
         m_b_last_excute=false;
24 
         m_b_last_branch=false;
25 
 
26 
#if defined(DEBUG)
27 
        flush_number=0;
28 
#endif
29 
        m_Rn=REGS(0);
30 
    SC_METHOD(entry);
31 
        sensitive_pos<<in_b_Clock;
32 
        SC_METHOD(shift_delay);
33 
        SC_METHOD(middle);
34 
        SC_METHOD(out);
35 
        SC_METHOD(out_delay);
36 
        SC_METHOD(alu_delay);
37 
        SC_METHOD(delay1);
38 
        SC_METHOD(delay2);
39 
        SC_METHOD(delay3);
40 
        SC_METHOD(write_lr);
41 
 
42 
 
43 
        mult(s_A_Mult,s_B_Mult,s_mult_out);
44 
 
45 
        bsh(s_shift_in,s_shift_type,s_shift_dist,s_shift_out,s_carry,out_b_RW,out_REG,inout_n_Data);
46 
 
47 
        alu(s_OP,s_A,s_B,s_alu_out,s_n_CPSR);
48 
}
49 
 
50 
scEX::~scEX()
51 
{
52 
}
53 
 
54 
void scEX::entry()
55 
{
56 
 
57 
        m_predict=in_branch_taken;
58 
                m_b_interrupt=in_interrupt;
59 
        m_b_is_mrt=in_b_is_mrt;
60 
                m_COND=in_COND;
61 
                m_A=in_A;
62 
            m_B=in_B;
63 
                m_Rd=in_Rd;
64 
        m_Rn=in_Rn;
65 
        m_OP=in_OP;
66 
        m_SET=in_SET;
67 
            m_b_S=in_b_S;
68 
            m_SHIFT_TYPE=in_SHIFT_TYPE;
69 
            m_n_Dist=in_n_Dist;
70 
 
71 
        m_b_M=in_b_M;
72 
    m_b_ls=in_b_ls;//is it load/store instruction
73 
    m_Rn=in_Rn; //base adress register
74 
        m_b_Pre=in_b_Pre;// alter base reg before?
75 
        m_b_Load=in_b_Load;// load or store
76 
    m_b_WB=in_b_WB;  //if i should write back to base reg?
77 
        m_is_Rm=is_Rm;
78 
        m_Rm=in_Rm;
79 
        m_is_Rs=is_Rs;
80 
        m_Rs=in_Rs;
81 
        //forwarding
82 
        m_is_write_Rd=in_is_write_Rd;
83 
        m_Rd_from_mem=in_Rd_from_mem;//target
84 
        m_n_Result_from_mem=in_n_Result_from_mem;
85 
        m_b_WB_from_mem=in_b_WB_from_mem;
86 
        m_Rn_from_mem=in_Rn_from_mem;//write-back register
87 
        m_n_Rn_from_mem=in_n_Rn_from_mem; //write-back data
88 
        //cout<<"exe0 Rd r="<<in_Rd_from_mem<<":"<<in_n_Result_from_mem<<endl;//target
89 
        //
90 
        //cout<<"stage1a: a="<<m_A<<" b="<<m_B<<" shift="<<m_n_Dist<<endl;
91 
 
92 
    forwarding_pc();
93 
 
94 
 
95 
 
96 
 
97 
   //display();
98 
 
99 
 trigger01_ex.notify(SC_ZERO_TIME);//trigger shift_delay()
100 
 
101 
}
102 
 
103 
void scEX::out(  )
104 
{
105 
 
106 
  next_trigger(trigger4);
107 
    //  cout<<"reslut="<<s_alu_out<<endl;
108 
 if((m_b_excute)||(m_Rd==R_PC))
109 
 {
110 
         //cout<<"entry"<<endl;
111 
        uint32_t temp;
112 
     out_Rd=m_Rd;
113 
 
114 
     //branch
115 
         if(m_Rd==R_PC)
116 
     {
117 
                        out_REG=R_PC;
118 
                        temp=inout_n_Data;
119 
            if(m_b_excute==1)
120 
                        {
121 
                                out_REG=R_PC;
122 
                                temp=inout_n_Data;
123 
                                if(m_b_excute==m_predict)
124 
                                {
125 
                                        m_b_branch=1;
126 
                                //      cout<<"exe   c w"<<endl;
127 
                            m_n_Result=s_alu_out;
128 
                                }
129 
                                else{
130 
                                //      cout<<"exe  e w"<<endl;
131 
                    m_n_Result=s_alu_out;
132 
                                        //cout<<"m_n_Result="<<m_n_Result<<endl;
133 
                                        m_b_branch=1;
134 
                                        //cout<<"  dont write Pc ex=1"<<endl;
135 
                                }
136 
                                 if(m_b_WB&&m_b_branch)//bl wirte r14
137 
                                 {
138 
                                   //read old pc
139 
                                        //out_b_RW=0;
140 
                                                out_REG=R_PC;
141 
                                                temp=inout_n_Data;
142 
                                        //write to link reg
143 
                                        //can not work correctly, should debug
144 
                                //      out_b_RW_link=1;
145 
                                        out_REG_link=R_LR;
146 
                                        inout_n_Data_link=temp-4;
147 
                                        trigger_write_lr.notify(SC_ZERO_TIME);
148 
                                }
149 
 
150 
                }else if((m_b_excute==0)&&(m_Rd==R_PC))
151 
                {
152 
                                        //;
153 
                        //cout<<"   b dont excute"<<endl;
154 
                        out_REG=R_PC;
155 
                        temp=inout_n_Data;
156 
 
157 
                        if(m_b_excute==m_predict)
158 
                        {
159 
                                        //cout<<"nexe c w"<<endl;
160 
                                        m_b_branch=0;
161 
                                        m_n_Result=s_alu_out;
162 
 
163 
 
164 
                        }
165 
                        else{
166 
                                //      cout<<"nexe e w"<<endl;
167 
                                        m_b_branch=1;
168 
                                        if(m_predict==1)
169 
                    {
170 
                                                ///cout<<"predict=1";
171 
                                                //cout<<" write Pc ex=0"<<endl;
172 
                                                m_n_Result=temp-4;
173 
                                        }else
174 
                                        {
175 
                                          //  cout<<"predict=0";
176 
                                                //cout<<" write Pc ex=0"<<endl;
177 
                                                m_n_Result=s_alu_out;
178 
                                        }
179 
                        }
180 
 
181 
                }
182 
 
183 
                m_b_last_branch=m_b_branch;
184 
            out_b_hold=m_b_hold;
185 
         }else
186 
         {
187 
                 //cout<<"branch=0"<<endl;
188 
                m_n_Result=s_alu_out;
189 
            m_b_branch=0;
190 
                m_b_last_branch=0;
191 
                m_b_hold=0;
192 
 
193 
         }
194 
          out_b_hold=m_b_hold;
195 
 
196 
        out_n_Result=m_n_Result;
197 
    out_b_Branch=m_b_branch;
198 
     out_b_excute=m_b_excute;
199 
         out_b_ls=m_b_ls;
200 
      out_Rn=m_Rn; //base adress register
201 
 
202 
     out_n_Rn=m_A;//content of base addr reg
203 
 
204 
     out_b_Pre=m_b_Pre;// alter base reg before?
205 
         out_b_Load=m_b_Load;// load or store
206 
     out_b_WB= m_b_WB;  //if i should write back to base reg?
207 
      out_is_mrt=m_b_is_mrt;
208 
         out_interrupt=m_b_interrupt&&m_b_excute;
209 
 
210 
 
211 
        // out_b_write_Rd=(m_Rd!=R_PC)&&(m_b_ls)&&(m_OP!=OP_TEQ)&&(m_OP!=OP_TST)&&(m_OP!=OP_CMP)&&(m_OP!=OP_CMN);
212 
 
213 
  out_b_write_Rd=(m_OP!=OP_TEQ)&&(m_OP!=OP_TST)&&(m_OP!=OP_CMP)&&(m_OP!=OP_CMN);
214 
 
215 
 
216 
         //save for forwarding()
217 
 
218 
         m_last_Result=s_alu_out;
219 
         m_b_last_ls=m_b_ls;
220 
         m_last_Rd=m_Rd;
221 
         m_last_Rn=m_Rn;
222 
         m_b_last_WB=m_b_WB;
223 
         m_b_last_is_Rs=m_is_Rs;
224 
         m_b_last_is_Rm=m_is_Rm;
225 
         m_last_OP=m_OP;
226 
         m_b_last_Load=m_b_Load;
227 
         m_b_last_excute=m_b_excute;
228 
         //cout<<"stage3:result"<<s_alu_out<<endl;
229 
 
230 
                  //set CPSR
231 
         if((m_SET==1)&&(m_Rd!=R_PC)){
232 
       //s_carry
233 
                 /*The logical
234 
operations (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) perform the logical action
235 
on all corresponding bits of the operand or operands to produce the result.
236 
If the S bit is set (and Rd is not R15, see below) the V flag in the CPSR will be unaffected, the C
237 
flag will be set to the carry out from the barrel shifter (or preserved when the shift
238 
operation is LSL #0), the Z flag will be set if and only if the result is all zeros, and the
239 
N flag will be set to the logical value of bit 31 of the result.
240 
                */
241 
 
242 
                 if((m_OP==OP_AND)||(m_OP==OP_EOR)||(m_OP==OP_TST)||(m_OP==OP_TEQ)||(m_OP==OP_ORR)||(m_OP==OP_BIC)||(m_OP==OP_MVN)||(m_OP==OP_MOV))
243 
                 {
244 
                         //cout<<"logic op "<<hex<<m_n_CPSR<<endl;
245 
                         //logic op
246 
                        if(!((m_SHIFT_TYPE==S_LSL)&&(m_n_Dist==0)))
247 
                        {
248 
                     if(s_carry==1)
249 
                         {
250 
                                 m_n_CPSR=m_n_CPSR|C_FLAG;
251 
                         };
252 
                         if(s_alu_out==0)
253 
                         {
254 
                                 m_n_CPSR=m_n_CPSR|Z_FLAG;
255 
                         };
256 
                         uint32_t temp=s_n_CPSR;
257 
                         temp=temp>>31;
258 
                         m_n_CPSR=temp?(m_n_CPSR|N_FLAG):(m_n_CPSR);
259 
                        }
260 
 
261 
                 }else
262 
                 {
263 
                         //arithmetic operations (SUB, RSB, ADD, ADC, SBC, RSC, CMP, CMN)
264 
 
265 
                      m_n_CPSR=s_n_CPSR;
266 
 
267 
                 }
268 
 
269 
 
270 
                inout_n_Data=m_n_CPSR;
271 
                 //cout<<"CPSddR "<<hex<<m_n_CPSR<<endl;
272 
                  trigger5.notify(SC_ZERO_TIME);
273 
 
274 
         }
275 
 
276 
         if(m_b_ls)//If is it a load/store instruction?
277 
         {
278 
 
279 
                if(!m_b_Load)//store Rd to memory
280 
                {
281 
                        //out_b_RW=0;
282 
                        out_REG=m_Rd;
283 
                        out_n_Rd=inout_n_Data;
284 
                 }
285 
        }
286 
 }else
287 
 {
288 
         out_b_Branch=0;
289 
                out_b_excute=0;
290 
        //cout<<endl;
291 
 
292 
 }//is excute;
293 
 
294 
}
295 
 
296 
void scEX::middle()
297 
{
298 
 
299 
next_trigger(trigger2);
300 
 // cout<<"middle:";
301 
if(m_b_excute||(m_Rd==R_PC))
302 
{
303 
        //CPSR
304 
                //out_b_RW=0;
305 
                out_REG=R_CPSR;
306 
                m_n_CPSR=inout_n_Data;
307 
                s_n_CPSR=m_n_CPSR;
308 
      //controls of ALU
309 
                s_OP=m_OP;
310 
        if(m_b_M)
311 
        {
312 
                s_A=s_mult_out;
313 
 
314 
        }else {
315 
                s_A=m_A;
316 
 
317 
        }
318 
 
319 
        if(m_b_S)
320 
    {
321 
                s_B=s_shift_out;
322 
                //cout<<"stage2: shifted value="<<s_shift_out<<endl;
323 
 
324 
        }else
325 
        {
326 
 
327 
           s_B=m_B;
328 
 
329 
        }
330 
}
331 
 
332 
 
333 
   trigger3.notify(SC_ZERO_TIME);//trigger alu_delay();
334 
 
335 
}
336 
 
337 
void scEX::shift_delay()
338 
{
339 
  next_trigger(trigger1);
340 
  trigger2.notify(SC_ZERO_TIME);//trigger middle();
341 
}
342 
 
343 
void scEX::alu_delay()
344 
{
345 
  next_trigger(trigger3);
346 
  trigger4.notify(SC_ZERO_TIME);//trigger out()
347 
 
348 
}
349 
bool scEX::is_excute(COND cond,uint32_t flag)
350 
{
351 
   switch (cond)
352 
    {
353 
    case C_EQ: return ((flag & Z_FLAG) ? TRUE : FALSE); break;
354 
    case C_NE: return ((flag & Z_FLAG) ? FALSE : TRUE); break;
355 
    case C_CS: return ((flag & C_FLAG) ? TRUE : FALSE); break;
356 
    case C_CC: return ((flag & C_FLAG) ? FALSE : TRUE); break;
357 
    case C_MI: return ((flag & N_FLAG) ? TRUE : FALSE); break;
358 
    case C_PL: return ((flag & N_FLAG) ? FALSE : TRUE); break;
359 
    case C_VS: return ((flag & V_FLAG) ? TRUE : FALSE); break;
360 
    case C_VC: return ((flag & V_FLAG) ? FALSE : TRUE); break;
361 
    case C_HI: return ((flag & CZ_FLAGS) == C_FLAG); break;
362 
    case C_LS: return ((flag & C_FLAG) == 0) ||
363 
                 ((flag & Z_FLAG) == Z_FLAG); break;
364 
    case C_GE: return (((flag & NV_FLAGS) == 0) ||
365 
                     ((flag & NV_FLAGS) == NV_FLAGS)); break;
366 
    case C_LT: return (((flag & NV_FLAGS) == V_FLAG) ||
367 
                     ((flag & NV_FLAGS) == N_FLAG)); break;
368 
    case C_GT: return (((flag & Z_FLAG) == 0) &&
369 
                     (((flag & NV_FLAGS) == NV_FLAGS) ||
370 
                      ((flag & NV_FLAGS) == 0))); break;
371 
    case C_LE: return (((flag & Z_FLAG) == Z_FLAG) ||
372 
                     (((flag & NV_FLAGS) == V_FLAG) ||
373 
                      ((flag & NV_FLAGS) == N_FLAG))); break;
374 
    case C_AL: return TRUE; break;
375 
    case C_NV: return FALSE; break;
376 
    default:
377 
       cout<<"error:"<<endl;
378 
        // Should never reach here
379 
           sc_stop();
380 
  }
381 
        // Should never reach here
382 
        return TRUE;
383 
}
384 
 
385 
 
386 
void scEX::display()
387 
{
388 
 
389 
  if(m_last_Rd==R_PC){
390 
    flush_number=2;
391 
        m_last_Rd=R_R0;
392 
  }
393 
  if(flush_number<=0)
394 
  {
395 
        //read CPSR
396 
      uint32_t R=0;
397 
                //      out_b_RW=0;
398 
                out_REG=R_PC;
399 
                R=inout_n_Data;
400 
          cout<<"       PC:"<<R;//0100
401 
                //out_b_RW=0;
402 
                out_REG=R_CPSR;
403 
                R=inout_n_Data;
404 
          cout<<" CPSR:";//0100
405 
  // Bit masks for CPSR
406 
    if((R&N_FLAG)==N_FLAG) cout<<"N";else cout<<"n";
407 
    if((R&Z_FLAG)==Z_FLAG) cout<<"Z"; else cout<<"z";
408 
    if((R&C_FLAG)==C_FLAG) cout<<"C"; else cout<<"c";
409 
    if((R&V_FLAG)==V_FLAG) cout<<"V"; else cout<<"v";
410 
        cout<<"  ";
411 
   cout<<(is_excute(in_COND,R)?"yes":" nop")<<endl;
412 
 
413 
  }else{
414 
 
415 
        flush_number--;
416 
 
417 
  }
418 
 
419 
}
420 
 
421 
void scEX::forwarding()
422 
{
423 
 
424 
if((m_b_last_excute==1))
425 
{
426 
 
427 
 
428 
        //if writing Rd,forwarding from EX out
429 
        //TEQ, TST, CMP & CMN
430 
         if((m_b_last_ls!=1)&&((m_last_OP!=OP_TEQ)&&(m_last_OP!=OP_TST)&&(m_last_OP!=OP_CMP)&&(m_last_OP!=OP_CMN)))
431 
        {
432 
              //Rn
433 
               if((m_Rn!=R_PC)&&(m_Rn==m_last_Rd))
434 
                   {
435 
               //cout<<"forwarding0 Rn r"<<m_Rn<<"="<<m_last_Result<<endl;
436 
                       m_A=m_last_Result;
437 
                   }
438 
        //Rm
439 
                        if((m_Rm!=R_PC)&&(m_is_Rm)&&(m_Rm==m_last_Rd)&&(m_b_last_is_Rm))
440 
                        {
441 
                           m_B=m_last_Result;
442 
 
443 
                        }
444 
        //Rs
445 
                        if((m_Rs!=R_PC)&&(m_is_Rs)&&(m_Rs==m_last_Rd)&&(m_b_last_is_Rs))
446 
                        {
447 
                          m_n_Dist=m_last_Result;
448 
                        }
449 
        }
450 
     if(m_b_last_WB==1)
451 
         {
452 
              //Rn
453 
               if((m_Rn!=R_PC)&&(m_Rn==m_last_Rn))
454 
                   {
455 
                       m_A=m_last_Result;
456 
                   }
457 
        //Rm
458 
                        if((m_Rm!=R_PC)&&(m_is_Rm)&&(m_Rm==m_last_Rn)&&m_b_last_is_Rm)
459 
                        {
460 
                           m_B=m_last_Result;
461 
 
462 
                        }
463 
        //Rs
464 
                        if((m_Rs!=R_PC)&&(m_is_Rs)&&(m_Rs==m_last_Rn)&&m_b_last_is_Rs)
465 
                        {
466 
                          m_n_Dist=m_last_Result;
467 
                        }
468 
 
469 
         }
470 
 
471 
 
472 
 
473 
 
474 
}//is excute?
475 
 
476 
 
477 
}
478 
 
479 
void scEX::regs()
480 
{
481 
         cout<<"EX"<<endl;
482 
        uint32_t R=0;
483 
         cout<<"        ";
484 
                for(int i=0;i<16;i++)
485 
                {
486 
 
487 
                     //out_b_RW=0;
488 
                     out_REG=REGS(i);
489 
                     R=inout_n_Data;
490 
                         cout<<"r"<<i<<"="<<R<<" ";
491 
                         if((i==4)||(i==9)) cout<<endl<<"       ";
492 
                }
493 
                //cout<<endl;
494 
 
495 
 
496 
}
497 
 
498 
void scEX::out_delay( )
499 
{
500 
        next_trigger(trigger5);
501 
 
502 
     if((m_SET==1)&&(m_Rd!=R_PC)){
503 
                out_b_RW=1;
504 
            out_REG=R_CPSR;
505 
                inout_n_Data=m_n_CPSR;
506 
         }
507 
 
508 
}
509 
 
510 
void scEX::forwarding1()
511 
{
512 
 
513 
  // cout<<" forwarding1 Rd_from_mem"<<m_Rd_from_mem<<endl;
514 
 
515 
if(m_Rd_from_mem!=R_PC)
516 
{
517 
   //  cout<<"in_Rd_from_mem=PC"<<in_Rd_from_mem<<endl;
518 
 
519 
         if(m_is_write_Rd==1)
520 
        {
521 
 
522 
      if((m_Rn!=R_PC)&&(m_Rn==m_Rd_from_mem))
523 
                   {
524 
 
525 
                       m_A=m_n_Result_from_mem;
526 
 
527 
                   }
528 
        //Rm
529 
                        if(((m_Rm!=R_PC)&&m_is_Rm)&&(m_Rm==m_Rd_from_mem))
530 
                        {
531 
 
532 
                           m_B=m_n_Result_from_mem;
533 
 
534 
                        }
535 
        //Rs
536 
                        if(((m_Rs!=R_PC)&&m_is_Rs)&&(m_Rs==m_Rd_from_mem))
537 
                        {
538 
                          m_n_Dist=m_n_Result_from_mem;
539 
                        }
540 
        }
541 
     if( m_b_WB_from_mem==1)
542 
         {
543 
 
544 
                  //cout<<" Rn:r"<<in_Rn_from_mem<<"="<<in_n_Rn_from_mem<<endl;
545 
                 //Rn
546 
               if(((m_Rn!=R_PC))&&(m_Rn==m_Rn_from_mem))
547 
                   {
548 
                       m_A=m_n_Result_from_mem;;
549 
                   }
550 
        //Rm
551 
                        if(((m_Rm!=R_PC)&&m_is_Rm)&&(m_Rm==m_Rn_from_mem))
552 
                        {
553 
                           m_B=m_n_Result_from_mem;;
554 
 
555 
                        }
556 
        //Rs
557 
                        if(((m_Rs!=R_PC)&&m_is_Rs)&&(m_Rs==m_Rn_from_mem))
558 
                        {
559 
                          m_n_Dist=m_n_Result_from_mem;;
560 
                        }
561 
 
562 
         }
563 
}//dont forward pc
564 
 
565 
}
566 
 
567 
void scEX::delay1( )
568 
{
569 
        next_trigger(trigger01_ex);
570 
        //forwarding
571 
 
572 
 
573 
 
574 
  trigger02_ex.notify(SC_ZERO_TIME);
575 
 
576 
}
577 
 
578 
void scEX::delay2()
579 
{
580 
        next_trigger(trigger02_ex);
581 
        //read CPSR
582 
        //out_b_RW=0;
583 
/*
584 
 out_REG=REGS(0);
585 
  uint32_t temp=inout_n_Data;
586 
  cout<<"       ex r0="<<temp;
587 
    out_REG=REGS(1);
588 
   temp=inout_n_Data;
589 
  cout<<" ex r1="<<temp;
590 
      out_REG=REGS(2);
591 
   temp=inout_n_Data;
592 
  cout<<" ex r2="<<temp;
593 
    out_REG=REGS(3);
594 
   temp=inout_n_Data;
595 
  cout<<" ex r3="<<temp<<endl;
596 
  */
597 
        //last_half();
598 
   //forwarding_pc();
599 
 
600 
  last_half();
601 
       forwarding();
602 
     forwarding1();
603 
 
604 
        out_REG=R_CPSR;
605 
        m_n_CPSR=inout_n_Data;
606 
    m_b_excute=is_excute(m_COND,m_n_CPSR);
607 
 
608 
    out_b_excute=m_b_excute;
609 
 
610 
        //m_b_interrupt=m_b_interrupt;
611 
        m_b_excute=m_b_excute&&(!m_b_interrupt);
612 
        if((m_b_is_mrt==1)&&(m_b_excute==1))
613 
        {
614 
                m_b_hold=1;
615 
            out_b_hold=1;
616 
 
617 
        }else
618 
        {
619 
            m_b_hold=0;
620 
                out_b_hold=0;
621 
 
622 
        }
623 
    trigger03_ex.notify(SC_ZERO_TIME);
624 
 
625 
}
626 
 
627 
void scEX::delay3()
628 
{
629 
        next_trigger(trigger03_ex);
630 
 
631 
 
632 
 
633 
//cout<<"stage1b: op="<<m_OP<<" m_A="<<m_A<<" b="<<m_B<<" shift="<<m_n_Dist<<endl;
634 
 
635 
//      cout<<(m_b_excute?"yes":"nop")<<endl;
636 
 
637 
        #if defined(DEBUG)
638 
//              display();
639 
    #endif
640 
if(m_b_excute||(m_Rd==R_PC))
641 
{
642 
 
643 
 
644 
    //cout<<(m_b_excute?"m_b_excute=1":"m_b_excute=0");
645 
 
646 
  if(m_b_M)//is it multi instruction
647 
  {
648 
      s_A_Mult=m_n_Dist;  //use dist signal to transfer rs
649 
          s_B_Mult=m_A;       //Rm
650 
  }
651 
  if(m_b_S) //Does it need to be shifted?
652 
  {
653 
                s_shift_type=m_SHIFT_TYPE;
654 
                s_shift_dist=m_n_Dist;
655 
                s_shift_in=m_B; //input to shifter
656 
       // cout<<" shift excuted"<<m_n_Dist<<endl;
657 
 
658 
 
659 
  }
660 
        //trigger1.notify(SC_ZERO_TIME);//trigger shift_delay()
661 
 }
662 
 else
663 
 {
664 
  out_b_Branch=0;
665 
  out_n_Result=0;
666 
  //out_b_RW=0;
667 
  out_b_WB=0;
668 
  out_b_excute=m_b_excute;
669 
 
670 
  //trigger4.notify(SC_ZERO_TIME);
671 
 }//is excute?
672 
trigger1.notify(SC_ZERO_TIME);//trigger shift_delay()
673 
}
674 
 
675 
void scEX::forwarding_pc()
676 
{
677 
        //if read pc
678 
        if((m_Rn==R_PC))
679 
        {
680 
                 out_REG=R_PC;
681 
 
682 
                //cout<<"forwarding rn="<<in_Rn<<":"<<inout_n_Data<<endl;
683 
                if((m_b_last_branch==1)||(m_last_Rd==R_PC))
684 
                {
685 
                 out_REG=R_PC;
686 
                 m_A=inout_n_Data;
687 
                }else
688 
                {
689 
                 out_REG=R_PC;
690 
                 m_A=inout_n_Data;
691 
                }
692 
                // cout<<"m_A="<<endl;
693 
 
694 
        }
695 
        if((m_Rm==R_PC)&&(m_is_Rm))
696 
        {
697 
        //      cout<<"Rm"<<in_Rm<<endl;
698 
                if( (m_b_last_branch==1)||(m_last_Rd==R_PC))
699 
                {
700 
                      out_REG=R_PC;
701 
                      m_B=inout_n_Data;
702 
                    //m_B=m_last_Result;
703 
                }else
704 
                {
705 
             out_REG=R_PC;
706 
                 m_B=inout_n_Data;
707 
                // cout<<"m_B="<<endl;
708 
                }
709 
        }
710 
        if((m_Rs==R_PC)&&(m_is_Rs))
711 
        {
712 
                //cout<<"Rs"<<in_Rs<<endl;
713 
                if( (m_b_last_branch==1)||(m_last_Rd==R_PC))
714 
                {
715 
                         out_REG=R_PC;
716 
                 m_n_Dist=inout_n_Data;
717 
                   // m_n_Dist=m_last_Result;
718 
                }else
719 
                {
720 
                out_REG=R_PC;
721 
                m_n_Dist=inout_n_Data;
722 
                //cout<<"m_DIST="<<endl;
723 
                }
724 
        }
725 
}
726 
 
727 
void scEX::delay0()
728 
{
729 
 
730 
}
731 
 
732 
void scEX::last_half()
733 
{
734 
   //cout<<" last half"<<m_Rd_from_mem<<endl;
735 
 
736 
if(in_Rd_from_mem!=R_PC)
737 
{
738 
   //  cout<<"in_Rd_from_mem=PC"<<in_Rd_from_mem<<endl;
739 
 
740 
         if(in_is_write_Rd==1)
741 
        {
742 
 
743 
                //cout<<"forwarding ..."<<endl;
744 
                 //cout<<m_is_Rm<<" in_Rn="<<m_Rn<<" in_Rm="<<m_Rm<<"  forwarding1 Rd:r"<<m_Rd_from_mem<<"="<<m_n_Result_from_mem<<endl;
745 
 
746 
      if((m_Rn!=R_PC)&&(m_Rn==in_Rd_from_mem))
747 
                   {
748 
 
749 
                       m_A=in_n_Result_from_mem;
750 
           //cout<<"last half m_A="<<m_A<<endl;
751 
                   }
752 
        //Rm
753 
                        if(((m_Rm!=R_PC)&&m_is_Rm)&&(m_Rm==in_Rd_from_mem))
754 
                        {
755 
 
756 
                           m_B=in_n_Result_from_mem;
757 
        //                 cout<<"last half m_B="<<m_B<<endl;
758 
                        }
759 
        //Rs
760 
                        if(((m_Rs!=R_PC)&&m_is_Rs)&&(m_Rs==in_Rd_from_mem))
761 
                        {
762 
                          m_n_Dist=in_n_Result_from_mem;
763 
                        }
764 
        }
765 
     if( in_b_WB_from_mem==1)
766 
         {
767 
 
768 
                  //cout<<" Rn:r"<<in_Rn_from_mem<<"="<<in_n_Rn_from_mem<<endl;
769 
                 //Rn
770 
               if(((m_Rn!=R_PC))&&(m_Rn==in_Rn_from_mem))
771 
                   {
772 
                       m_A=in_n_Result_from_mem;;
773 
                   }
774 
        //Rm
775 
                        if(((m_Rm!=R_PC)&&m_is_Rm)&&(m_Rm==in_Rn_from_mem))
776 
                        {
777 
                           m_B=in_n_Result_from_mem;;
778 
 
779 
                        }
780 
        //Rs
781 
                        if(((m_Rs!=R_PC)&&m_is_Rs)&&(m_Rs==in_Rn_from_mem))
782 
                        {
783 
                          m_n_Dist=in_n_Result_from_mem;;
784 
                        }
785 
 
786 
         }
787 
}//dont forward pc
788 
}
789 
 
790 
void scEX::write_lr()
791 
{
792 
  next_trigger(trigger_write_lr);
793 
                out_b_RW_link=1;
794 
                out_REG_link=R_LR;
795 
        //      inout_n_Data=temp-4;
796 
}

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