URL https://opencores.org/ocsvn/scarm/scarm/trunk

Subversion Repositories scarm

[/] [scarm/] [trunk/] [src/] [Instructions/] [scARMLSI.cpp] - Blame information for rev 10

Go to most recent revision | Details | Compare with Previous | View Log


// scARMLSI.cpp: implementation of the scARMULSI class.
//
//////////////////////////////////////////////////////////////////////
 
#include "scARMLSI.h"
 
//////////////////////////////////////////////////////////////////////
// Construction/Destruction
//////////////////////////////////////////////////////////////////////
 
scARMLSI::scARMLSI()
{
 
}
 
scARMLSI::~scARMLSI()
{
 
}
 
REGS scARMLSI::get_Rn(uint32_t nI)
{
        REGS r;
   uint32_t nR;
   //0000,0001,1110,0000,0000,0000,0000,0000
   //
   nR=((nI>>16)&0x0000000f);
 
   switch(nR)
   {
   case 0x0:{r=R_R0;break;}
   case 0x1:{r=R_R1;break;}
   case 0x2:{r=R_R2;break;}
   case 0x3:{r=R_R3;break;}
   case 0x4:{r=R_R4;break;}
   case 0x5:{r=R_R5;break;}
   case 0x6:{r=R_R6;break;}
   case 0x7:{r=R_R7;break;}
   case 0x8:{r=R_R8;break;}
   case 0x9:{r=R_R9;break;}
   case 0xa:{r=R_R10;break;}
   case 0xb:{r=R_FP;break;}
   case 0xc:{r=R_IP;break;}
   case 0xd:{r=R_SP;break;}
   case 0xe:{r=R_LR;break;}
   case 0xf:{r=R_PC;break;}
   default: {cout<<"can not access the Rn"<<endl;}
   }
   return r;
}
 
REGS scARMLSI::get_Rm(uint32_t nI)
{
        REGS r;
   uint32_t nR;
  //0000,0000,0000,0000,0000,0000,0000,0000
   nR=(nI&0x0000000f);
   switch(nR)
   {
   case 0x0:{r=R_R0;break;}
   case 0x1:{r=R_R1;break;}
   case 0x2:{r=R_R2;break;}
   case 0x3:{r=R_R3;break;}
   case 0x4:{r=R_R4;break;}
   case 0x5:{r=R_R5;break;}
   case 0x6:{r=R_R6;break;}
   case 0x7:{r=R_R7;break;}
   case 0x8:{r=R_R8;break;}
   case 0x9:{r=R_R9;break;}
   case 0x10:{r=R_R10;break;}
   case 0x11:{r=R_FP;break;}
   case 0x12:{r=R_IP;break;}
   case 0x13:{r=R_SP;break;}
   case 0x14:{r=R_LR;break;}
   case 0x15:{r=R_PC;break;}
  default: {cout<<"can not access Rm"<<endl;}
   }
   return r;
}
 
uint32_t scARMLSI::get_Imm(uint32_t nI)
{
        uint32_t i;
        i=nI&0xffff;
        //signed extended
        if(((nI>>15)&0x1)==1)
        {i=0xffff0000+i;}
    return i;
}
 
SHIFT scARMLSI::get_shift(uint32_t nI)
{
   SHIFT s;
   //
   uint32_t nS;
  //0000,0000,0000,0000,0000,0000,0000,0000
   nS=(nI>>5)&0x3;
   switch(nS)
   {
   case 0x0:{s=S_LSL;break;}
   case 0x1:{s=S_LSR;break;}
   case 0x2:{s=S_ASR;break;}
   case 0x3:{s=S_ROR;break;}
   case 0x4:{s=S_RRX;break;}
   case 0x5:{s=S_ASL;break;}
 
  default: {cout<<"SHIFT Type error"<<endl;}
   }
   return s;
}
 
 
 
OPCODE scARMLSI::get_opcode(uint32_t nI)
{
  OPCODE op;
  // DPI_MASK    0x0C000000
  uint32_t nOp=(nI>>21)&0xf;
  switch(nOp)
  {
        case 0x00: { op=OP_AND; break;}
        case 0x01: { op=OP_EOR; break;}
        case 0x02: { op=OP_SUB; break;}
        case 0x03: { op=OP_RSB; break;}
        case 0x04: { op=OP_ADD; break;}
        case 0x05: { op=OP_ADC; break;}
        case 0x06: { op=OP_SBC; break;}
        case 0x07: { op=OP_RSC; break;}
        case 0x08: { op=OP_TST; break;}
        case 0x09: { op=OP_TEQ; break;}
        case 0x0a: { op=OP_CMP; break;}
        case 0x0b: { op=OP_CMN; break;}
        case 0x0c: { op=OP_ORR; break;}
        case 0x0d: { op=OP_MOV; break;}
        case 0x0e: { op=OP_BIC; break;}
        case 0x0f: { op=OP_MVN ; break;}
        default:{cout<<"unknown opcode"<<endl;}
  }
  return op;
}
 
 
 
REGS scARMLSI::get_Rd(uint32_t nI)
{
        REGS r;
   uint32_t nR;
  //0000,0000,0000,0000,0000,0000,0000,0000
   nR=(nI>>12)&0xf;
   switch(nR)
   {
   case 0x0:{r=R_R0;break;}
   case 0x1:{r=R_R1;break;}
   case 0x2:{r=R_R2;break;}
   case 0x3:{r=R_R3;break;}
   case 0x4:{r=R_R4;break;}
   case 0x5:{r=R_R5;break;}
   case 0x6:{r=R_R6;break;}
   case 0x7:{r=R_R7;break;}
   case 0x8:{r=R_R8;break;}
   case 0x9:{r=R_R9;break;}
   case 0xa:{r=R_R10;break;}
   case 0xb:{r=R_FP;break;}
   case 0xc:{r=R_IP;break;}
   case 0xd:{r=R_SP;break;}
   case 0xe:{r=R_LR;break;}
   case 0xf:{r=R_PC;break;}
 
   }
   return r;
}
 
uint32_t scARMLSI::get_shift_dist(uint32_t nI)
{
  uint32_t dist;
  dist=(nI>>7)&0x1f;
  return dist;
}
 
uint32_t scARMLSI::get_Rot(uint32_t nI)
{
        uint32_t rot;
        rot=(nI>>8)&0xf;
        return rot;
 
}
 
bool_t scARMLSI::get_Set(uint32_t nI)
{
  bool_t bit;
  bit=(nI>>20)&0x1;
  return bit;
}
 
REGS scARMLSI::get_Rs(uint32_t nI)
{
   REGS r;
   //
   uint32_t nS=nI;
   nS=(nI>>8)&0xf;
   switch(nS)
   {
   case 0x0:{r=R_R0;break;}
   case 0x1:{r=R_R1;break;}
   case 0x2:{r=R_R2;break;}
   case 0x3:{r=R_R3;break;}
   case 0x4:{r=R_R4;break;}
   case 0x5:{r=R_R5;break;}
   case 0x6:{r=R_R6;break;}
   case 0x7:{r=R_R7;break;}
   case 0x8:{r=R_R8;break;}
   case 0x9:{r=R_R9;break;}
   case 0xa:{r=R_R10;break;}
   case 0xb:{r=R_FP;break;}
   case 0xc:{r=R_IP;break;}
   case 0xd:{r=R_SP;break;}
   case 0xe:{r=R_LR;break;}
   default:{cout<<"error of shift register"<<endl;}
   }
   return r;
}

Browse

Tools

Subversion Repositories scarm

[/] [scarm/] [trunk/] [src/] [Instructions/] [scARMLSI.cpp] - Blame information for rev 10

Line No.	Rev	Author	Line
1	2	zhong	`// scARMLSI.cpp: implementation of the scARMULSI class.`
2			`//`
3			`//////////////////////////////////////////////////////////////////////`
4
5			`#include "scARMLSI.h"`
6
7			`//////////////////////////////////////////////////////////////////////`
8			`// Construction/Destruction`
9			`//////////////////////////////////////////////////////////////////////`
10
11			`scARMLSI::scARMLSI()`
12			`{`
13
14			`}`
15
16			`scARMLSI::~scARMLSI()`
17			`{`
18
19			`}`
20
21			`REGS scARMLSI::get_Rn(uint32_t nI)`
22			`{`
23			`REGS r;`
24			`uint32_t nR;`
25			`//0000,0001,1110,0000,0000,0000,0000,0000`
26			`//`
27			`nR=((nI>>16)&0x0000000f);`
28
29			`switch(nR)`
30			`{`
31			`case 0x0:{r=R_R0;break;}`
32			`case 0x1:{r=R_R1;break;}`
33			`case 0x2:{r=R_R2;break;}`
34			`case 0x3:{r=R_R3;break;}`
35			`case 0x4:{r=R_R4;break;}`
36			`case 0x5:{r=R_R5;break;}`
37			`case 0x6:{r=R_R6;break;}`
38			`case 0x7:{r=R_R7;break;}`
39			`case 0x8:{r=R_R8;break;}`
40			`case 0x9:{r=R_R9;break;}`
41			`case 0xa:{r=R_R10;break;}`
42			`case 0xb:{r=R_FP;break;}`
43			`case 0xc:{r=R_IP;break;}`
44			`case 0xd:{r=R_SP;break;}`
45			`case 0xe:{r=R_LR;break;}`
46			`case 0xf:{r=R_PC;break;}`
47			`default: {cout<<"can not access the Rn"<<endl;}`
48			`}`
49			`return r;`
50			`}`
51
52			`REGS scARMLSI::get_Rm(uint32_t nI)`
53			`{`
54			`REGS r;`
55			`uint32_t nR;`
56			`//0000,0000,0000,0000,0000,0000,0000,0000`
57			`nR=(nI&0x0000000f);`
58			`switch(nR)`
59			`{`
60			`case 0x0:{r=R_R0;break;}`
61			`case 0x1:{r=R_R1;break;}`
62			`case 0x2:{r=R_R2;break;}`
63			`case 0x3:{r=R_R3;break;}`
64			`case 0x4:{r=R_R4;break;}`
65			`case 0x5:{r=R_R5;break;}`
66			`case 0x6:{r=R_R6;break;}`
67			`case 0x7:{r=R_R7;break;}`
68			`case 0x8:{r=R_R8;break;}`
69			`case 0x9:{r=R_R9;break;}`
70			`case 0x10:{r=R_R10;break;}`
71			`case 0x11:{r=R_FP;break;}`
72			`case 0x12:{r=R_IP;break;}`
73			`case 0x13:{r=R_SP;break;}`
74			`case 0x14:{r=R_LR;break;}`
75			`case 0x15:{r=R_PC;break;}`
76			`default: {cout<<"can not access Rm"<<endl;}`
77			`}`
78			`return r;`
79			`}`
80
81			`uint32_t scARMLSI::get_Imm(uint32_t nI)`
82			`{`
83			`uint32_t i;`
84			`i=nI&0xffff;`
85			`//signed extended`
86			`if(((nI>>15)&0x1)==1)`
87			`{i=0xffff0000+i;}`
88			`return i;`
89			`}`
90
91			`SHIFT scARMLSI::get_shift(uint32_t nI)`
92			`{`
93			`SHIFT s;`
94			`//`
95			`uint32_t nS;`
96			`//0000,0000,0000,0000,0000,0000,0000,0000`
97			`nS=(nI>>5)&0x3;`
98			`switch(nS)`
99			`{`
100			`case 0x0:{s=S_LSL;break;}`
101			`case 0x1:{s=S_LSR;break;}`
102			`case 0x2:{s=S_ASR;break;}`
103			`case 0x3:{s=S_ROR;break;}`
104			`case 0x4:{s=S_RRX;break;}`
105			`case 0x5:{s=S_ASL;break;}`
106
107			`default: {cout<<"SHIFT Type error"<<endl;}`
108			`}`
109			`return s;`
110			`}`
111
112
113
114			`OPCODE scARMLSI::get_opcode(uint32_t nI)`
115			`{`
116			`OPCODE op;`
117			`// DPI_MASK 0x0C000000`
118			`uint32_t nOp=(nI>>21)&0xf;`
119			`switch(nOp)`
120			`{`
121			`case 0x00: { op=OP_AND; break;}`
122			`case 0x01: { op=OP_EOR; break;}`
123			`case 0x02: { op=OP_SUB; break;}`
124			`case 0x03: { op=OP_RSB; break;}`
125			`case 0x04: { op=OP_ADD; break;}`
126			`case 0x05: { op=OP_ADC; break;}`
127			`case 0x06: { op=OP_SBC; break;}`
128			`case 0x07: { op=OP_RSC; break;}`
129			`case 0x08: { op=OP_TST; break;}`
130			`case 0x09: { op=OP_TEQ; break;}`
131			`case 0x0a: { op=OP_CMP; break;}`
132			`case 0x0b: { op=OP_CMN; break;}`
133			`case 0x0c: { op=OP_ORR; break;}`
134			`case 0x0d: { op=OP_MOV; break;}`
135			`case 0x0e: { op=OP_BIC; break;}`
136			`case 0x0f: { op=OP_MVN ; break;}`
137			`default:{cout<<"unknown opcode"<<endl;}`
138			`}`
139			`return op;`
140			`}`
141
142
143
144			`REGS scARMLSI::get_Rd(uint32_t nI)`
145			`{`
146			`REGS r;`
147			`uint32_t nR;`
148			`//0000,0000,0000,0000,0000,0000,0000,0000`
149			`nR=(nI>>12)&0xf;`
150			`switch(nR)`
151			`{`
152			`case 0x0:{r=R_R0;break;}`
153			`case 0x1:{r=R_R1;break;}`
154			`case 0x2:{r=R_R2;break;}`
155			`case 0x3:{r=R_R3;break;}`
156			`case 0x4:{r=R_R4;break;}`
157			`case 0x5:{r=R_R5;break;}`
158			`case 0x6:{r=R_R6;break;}`
159			`case 0x7:{r=R_R7;break;}`
160			`case 0x8:{r=R_R8;break;}`
161			`case 0x9:{r=R_R9;break;}`
162			`case 0xa:{r=R_R10;break;}`
163			`case 0xb:{r=R_FP;break;}`
164			`case 0xc:{r=R_IP;break;}`
165			`case 0xd:{r=R_SP;break;}`
166			`case 0xe:{r=R_LR;break;}`
167			`case 0xf:{r=R_PC;break;}`
168
169			`}`
170			`return r;`
171			`}`
172
173			`uint32_t scARMLSI::get_shift_dist(uint32_t nI)`
174			`{`
175			`uint32_t dist;`
176			`dist=(nI>>7)&0x1f;`
177			`return dist;`
178			`}`
179
180			`uint32_t scARMLSI::get_Rot(uint32_t nI)`
181			`{`
182			`uint32_t rot;`
183			`rot=(nI>>8)&0xf;`
184			`return rot;`
185
186			`}`
187
188			`bool_t scARMLSI::get_Set(uint32_t nI)`
189			`{`
190			`bool_t bit;`
191			`bit=(nI>>20)&0x1;`
192			`return bit;`
193			`}`
194
195			`REGS scARMLSI::get_Rs(uint32_t nI)`
196			`{`
197			`REGS r;`
198			`//`
199			`uint32_t nS=nI;`
200			`nS=(nI>>8)&0xf;`
201			`switch(nS)`
202			`{`
203			`case 0x0:{r=R_R0;break;}`
204			`case 0x1:{r=R_R1;break;}`
205			`case 0x2:{r=R_R2;break;}`
206			`case 0x3:{r=R_R3;break;}`
207			`case 0x4:{r=R_R4;break;}`
208			`case 0x5:{r=R_R5;break;}`
209			`case 0x6:{r=R_R6;break;}`
210			`case 0x7:{r=R_R7;break;}`
211			`case 0x8:{r=R_R8;break;}`
212			`case 0x9:{r=R_R9;break;}`
213			`case 0xa:{r=R_R10;break;}`
214			`case 0xb:{r=R_FP;break;}`
215			`case 0xc:{r=R_IP;break;}`
216			`case 0xd:{r=R_SP;break;}`
217			`case 0xe:{r=R_LR;break;}`
218			`default:{cout<<"error of shift register"<<endl;}`
219			`}`
220			`return r;`
221			`}`