OpenCores
URL https://opencores.org/ocsvn/scarm/scarm/trunk

Subversion Repositories scarm

[/] [scarm/] [trunk/] [src/] [pipeline/] [scIF.h] - Blame information for rev 8

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 zhong
///////////////////////////////////////////////////////////////////////////////
2
// This program is free software; you can redistribute it and/or
3
// modify it under the terms of the GNU General Public License
4
// as published by the Free Software Foundation; either version 2
5
// of the License, or (at your option) any later version.
6
//
7
// This program is distributed in the hope that it will be useful,
8
// but WITHOUT ANY WARRANTY; without even the implied warranty of
9
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10
// GNU General Public License for more details.
11
//
12
// You should have received a copy of the GNU General Public License
13
// along with this program; if not, write to the Free Software
14
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
15
//////////////////////////////////////////////////////////////////////
16
 
17
///////////////////////////////////////////////////////////////////              
18
//          
19
//  Original Author: Allen Tao Zhong,
20
//  University of Electronic Science and Technology in China
21
//  email: zhong@opencores.org
22
//  info   This is a SystemC ARM model 
23
//   
24
//
25
///////////////////////////////////////////////////////////////////////////////
26
// scIF.h: interface for the scIF class.
27
//
28
//////////////////////////////////////////////////////////////////////
29
 
30
 
31
#include<systemc.h>
32
#include <sc_mslib.h>
33
#include "scTypes.h"
34
enum ARI {ARI_ALU, ARI_INC, ARI_REG, ARI_NONE};
35
class scIF:public sc_module
36
{
37
public: //ports
38
        sc_in<bool> in_b_Clock;
39
 
40
        sc_outmaster<uint32_t> out_n_Addr;//  address bus
41
        sc_inoutslave<uint32_t>  inout_n_Data; //Instruction bus
42
        sc_in<uint32_t>  in_n_PC;
43
        sc_out<uint32_t> out_n_Instruction;
44
        sc_out<uint32_t> out_n_NPC;
45
        sc_in<bool_t>    in_b_Flush;
46
 
47
public:
48
 
49
 
50
        SC_HAS_PROCESS(scIF);
51
        scIF(const sc_module_name name_):sc_module(name_)
52
        {
53
 
54
       //s_n_IR=0;//nop
55
 
56
           SC_METHOD(entry);
57
           sensitive_pos<<in_b_Clock;
58
 
59
       SC_METHOD(increase_pc);
60
           sensitive<<s_n_IR;
61
 
62
        }
63
        virtual ~scIF();
64
private:
65
        sc_signal<uint32_t> s_n_IR;
66
        sc_signal<uint32_t> s_n_NPC;
67
 
68
 
69
private:
70
        void increase_pc();
71
        uint32_t  read_mem_data(uint32_t);
72
        void entry(void);
73
 
74
};

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.