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[/] [scarm/] [trunk/] [src/] [scARMSoC.h] - Blame information for rev 10

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1 5 zhong
///////////////////////////////////////////////////////////////////////////////
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// This program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public License
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// as published by the Free Software Foundation; either version 2
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// of the License, or (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
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//////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////              
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//          
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//  Original Author: Allen Tao Zhong,
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//  University of Electronic Science and Technology in China
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//  email: zhong@opencores.org
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//  info   This is a SystemC ARM model 
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//   
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//
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///////////////////////////////////////////////////////////////////////////////
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/*****************************************************************************
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  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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  changes you are making here.
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      Name, Affiliation, Date:
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  Description of Modification:
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 *****************************************************************************/
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// scARMSoC.h: interface for the scARMSoC class.
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//
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//////////////////////////////////////////////////////////////////////
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#include<systemc.h>
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#include <sc_mslib.h>
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#include "scTypes.h"
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//components
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#include "scARMCore.h"
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#include "sc_mem_ch.h"
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class scARMSoC:public sc_module
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{
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public://ports
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        //sc_in<bool_t>        in_b_nRESET;
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        sc_in<bool>          in_b_Clock;
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        //link with memory 
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//      sc_port<sc_mem_ch> mem_ch;
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        sc_outmaster<bool>        out_b_nRW;
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        sc_outmaster<uint32_t>     out_n_A;
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        sc_inoutslave<uint32_t>   inout_n_D;
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 //***********************************
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 //  port unused        
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 //********************************
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//      sc_in<bool_t>        in_b_nIRQ;
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//      sc_in<bool_t>        in_b_nFIQ;
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//      sc_in<bool_t>        in_b_nBW;
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public:
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        void entry();
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        SC_HAS_PROCESS(scARMSoC);
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        scARMSoC(sc_module_name name_):sc_module(name_),
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                m_ARMCore("core")
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        {
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        //      SC_METHOD(entry);
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        //      sensitive_pos<<in_b_Clock;
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            m_ARMCore(in_b_Clock,out_b_nRW,out_n_A,inout_n_D);
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        };
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        virtual ~scARMSoC();
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private:
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        scARMCore m_ARMCore;
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};

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