OpenCores
URL https://opencores.org/ocsvn/scarm/scarm/trunk

Subversion Repositories scarm

[/] [scarm/] [trunk/] [src/] [scID.h] - Blame information for rev 8

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 zhong
///////////////////////////////////////////////////////////////////////////////
2
// This program is free software; you can redistribute it and/or
3
// modify it under the terms of the GNU General Public License
4
// as published by the Free Software Foundation; either version 2
5
// of the License, or (at your option) any later version.
6
//
7
// This program is distributed in the hope that it will be useful,
8
// but WITHOUT ANY WARRANTY; without even the implied warranty of
9
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10
// GNU General Public License for more details.
11
//
12
// You should have received a copy of the GNU General Public License
13
// along with this program; if not, write to the Free Software
14
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
15
//////////////////////////////////////////////////////////////////////
16
 
17
///////////////////////////////////////////////////////////////////              
18
//          
19
//  Original Author: Allen Tao Zhong,
20
//  University of Electronic Science and Technology in China
21
//  email: zhong@opencores.org
22
//  info   This is a SystemC ARM model 
23
//   
24
//
25
///////////////////////////////////////////////////////////////////////////////
26
// scID.h: interface for the scID class.
27
//
28
//////////////////////////////////////////////////////////////////////
29
#if !defined(SCID_H)
30
#define SCID_H
31
#include<systemc.h>
32
#include<sc_mslib.h>
33
#include "scTypes.h"
34
#include "scARMInstruction.h"
35
#include "scRegisterFile.h"
36
#include "scBarrelShifter.h"
37
#include "scSignExt.h"
38
#define DEBUG
39
//#include "Bus.h"
40
#include "scALU.h"
41
class scID : public sc_module
42
{
43
 
44
//      friend class scARMInstruction;
45
public: //ports
46
        sc_in<bool>     in_b_hold;
47
        sc_in<bool> in_b_Clock;
48
        sc_out<bool>  out_b_is_branch;
49
        sc_out<bool>  out_interrupt;
50
        sc_out<COND> out_COND;
51
        sc_out<bool> out_branch_taken;
52
        sc_in<bool> in_b_flush_2;
53
        sc_out<bool> out_b_flush;
54
 
55
        //IF to ID
56
        sc_in<uint32_t> in_n_Instruction;
57
        sc_in<uint32_t> in_n_PC;
58
        //regs
59
        sc_outmaster<bool>        out_b_RW;// 0-Read  1-Write
60
        sc_outmaster<REGS>     out_REG;
61
        sc_inoutslave<uint32_t> inout_n_Data;
62
//ID to EX
63
    //ABus 
64
        sc_out<uint32_t>   out_n_A;
65
    //BBus
66
        sc_out<uint32_t>   out_n_B;
67
    //controls of ALU
68
        sc_out<OPCODE>    out_OP;
69
    sc_out<bool>    out_SET;
70
        //controls of Barrel Shifter
71
         sc_out<bool>   out_b_S;
72
         sc_out<SHIFT>  out_SHIFT_TYPE;
73
          sc_out<bool>  out_b_is_mrt;
74
         sc_out<uint32_t>  out_n_Dist;
75
         //controls of Booth Multiplier
76
         sc_out<bool>   out_b_M;
77
         //controls to MEM
78
         sc_out<bool>   out_b_ls;
79
         sc_out<REGS>   out_Rn;
80
         sc_out<bool>   out_b_Pre;
81
         sc_out<bool>    out_b_Load;
82
     sc_out<bool>   out_b_WB;
83
        // target reg
84
    sc_out<REGS>    out_Rd;
85
    sc_out<REGS>    out_Rm;//used for forwarding
86
    sc_out<REGS>    out_Rs;
87
    sc_out<bool>    is_Rm;
88
        sc_out<bool>    is_Rs;
89
 
90
 
91
 
92
 
93
public:
94
        void delay2_1();
95
        bool predict();
96
        void delay0_1();
97
        void delay0();
98
        void delay3();
99
        void delay2();
100
        void delay1();
101
        void regs();
102
        void display();
103
        virtual  scARMInstruction* create_instru(uint32_t i);
104
        SC_HAS_PROCESS(scID);
105
        scID(const sc_module_name name_):sc_module(name_)
106
        //      ,       inst_SignExt("signext")
107
        {
108
       flush_number=0;
109
       save_flush=0;
110
           m_b_is_mrt=0;
111
           m_n_list=0;
112
           m_reg_in_list=0;
113
           m_order=0;
114
           m_index=0;
115
 
116
           SC_METHOD(entry);
117
           sensitive_pos<<in_b_Clock;
118
           SC_METHOD(delay0);
119
           SC_METHOD(delay0_1);
120
           SC_METHOD(delay1);
121
 
122
           SC_METHOD(delay2);
123
           SC_METHOD(delay2_1);
124
           SC_METHOD(delay3);
125
 
126
          // inst_SignExt(s_n_Dist,out_n_Dist);
127
 
128
        }
129
        virtual ~scID();
130
 
131
 
132
 
133
private:
134
 
135
//use the fixed field technique
136
 
137
        void entry();
138
private:
139
 bool save_flush;
140
  bool m_b_interrupt,m_b_is_mrt,m_b_up;
141
  uint32_t m_ir,m_pc,m_last_ir,m_last_pc,m_n_list,m_reg_in_list,m_index,m_order;
142
  sc_event trigger,trigger0,trigger0_1,trigger1,trigger2,trigger2_1,trigger3;
143
  uint32_t m_A,m_B,m_Dist;
144
  REGS     m_Rn,m_Rd,m_Rm,m_Rs;
145
  OPCODE   m_OP;
146
  COND     m_COND;
147
  SHIFT    m_SHIFT_TYPE;
148
  bool     m_b_predict,m_b_flush,m_b_S,m_b_ls,m_b_M,m_b_Pre,m_b_Load,m_b_WB,m_SET;
149
  bool     m_b_is_Rm,m_b_is_Rs;
150
private:
151
 
152
        //      scSignExt inst_SignExt;
153
        #if defined(DEBUG)
154
   sc_signal<uint32_t> s_reg_in_list;
155
  sc_signal<bool>     s_is_mrt;
156
  sc_signal<uint32_t> s_pc_debug;
157
  sc_signal <uint32_t>s_ir_debug;
158
  sc_signal <uint32_t>s_A_debug;
159
  sc_signal <uint32_t>s_B_debug;
160
  sc_signal <uint32_t>s_dist_debug;
161
  int flush_number;
162
  sc_signal<bool> s_b_flush_debug;
163
#endif
164
 
165
};
166
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.