OpenCores
URL https://opencores.org/ocsvn/scarm/scarm/trunk

Subversion Repositories scarm

[/] [scarm/] [trunk/] [src/] [scIF.cpp] - Blame information for rev 10

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 zhong
// scIF.cpp: implementation of the scIF class.
2
//
3
//////////////////////////////////////////////////////////////////////
4
 
5
#include "scIF.h"
6
#include "scRAM.h"
7
#define DEBUG
8
//////////////////////////////////////////////////////////////////////
9
// Construction/Destruction
10
//////////////////////////////////////////////////////////////////////
11
 
12
 
13
 
14
scIF::~scIF()
15
{
16
 
17
}
18
 
19
void scIF::entry()
20
{
21
 
22
            //regs();
23
    m_nPC=in_n_PC;
24
 
25
 
26
    trigger1_if.notify(SC_ZERO_TIME);
27
}
28
 
29
 
30
 
31
uint32_t  scIF::read_mem_data(uint32_t addr)
32
{
33
  //out_b_nRW=0;
34
  out_n_Addr=addr;
35
  return inout_n_Data;
36
}
37
 
38
 
39
 
40
 
41
void scIF::regs()
42
{
43
 
44
}
45
 
46
void scIF::delay1()
47
{
48
        next_trigger(trigger1_if);
49
 
50
        trigger2_if.notify(SC_ZERO_TIME);
51
}
52
 
53
void scIF::delay2()
54
{
55
   next_trigger(trigger2_if);
56
 
57
   trigger3_if.notify(SC_ZERO_TIME);
58
}
59
 
60
void scIF::delay3( )
61
{
62
 
63
        next_trigger(trigger3_if);
64
 
65
if(in_b_hold==0)
66
{
67
 
68
        if(m_nPC==0) cout<<"start..."<<endl;
69
        m_nIR=read_mem_data(m_nPC);
70
 
71
     out_n_PC=m_nPC;
72
                //stop machine
73
                if(m_nIR==(0x12345678)) sc_stop();
74
    if((in_b_flush==0)&&(in_b_flush_2==0))
75
        {
76
                        out_n_Instruction=m_nIR;
77
 
78
        }else
79
        {
80
                    out_n_Instruction=0xf1500000;
81
        }
82
 
83
}//hold
84
 
85
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.