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[/] [scarm/] [trunk/] [src/] [scIF.h] - Blame information for rev 5

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1 5 zhong
///////////////////////////////////////////////////////////////////////////////
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// This program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public License
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// as published by the Free Software Foundation; either version 2
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// of the License, or (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
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//////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////              
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//          
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//  Original Author: Allen Tao Zhong,
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//  University of Electronic Science and Technology in China
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//  email: zhong@opencores.org
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//  info   This is a SystemC ARM model 
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//   
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//
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///////////////////////////////////////////////////////////////////////////////
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// scIF.h: interface for the scIF class.
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//
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//////////////////////////////////////////////////////////////////////
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#include<systemc.h>
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#include <sc_mslib.h>
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#include "scTypes.h"
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#include "scRegisterFile.h"
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enum ARI {ARI_ALU, ARI_INC, ARI_REG, ARI_NONE};
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class scIF:public sc_module
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{
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public: //ports
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        sc_in<bool>     in_b_hold;
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        sc_in<bool> in_b_Clock;
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        sc_in<bool> in_b_flush;
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        sc_in<bool> in_b_flush_2;
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        sc_in<uint32_t>  in_n_PC;
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                //regs
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        sc_outmaster<bool>        out_b_RW_pc;// 0-Read  1-Write
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        sc_outmaster<REGS>     out_REG_pc;
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        sc_inoutslave<uint32_t> inout_n_Data_pc;
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        //Get Instruction
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        sc_outmaster<bool>  out_b_nRW;
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        sc_outmaster<uint32_t> out_n_Addr;//  address bus
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        sc_inoutslave<uint32_t>  inout_n_Data; //Instruction bus
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        sc_out<uint32_t> out_n_Instruction;
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        sc_out<uint32_t> out_n_PC;
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public:
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        void delay3( );
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        void delay2();
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        void delay1();
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        void regs();
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//      void out();
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        SC_HAS_PROCESS(scIF);
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        scIF(const sc_module_name name_):sc_module(name_)
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        {
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       m_b_start=true;
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           m_nIR=0;
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           m_nPC=0;
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       SC_METHOD(entry);
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           sensitive_pos<<in_b_Clock;
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           SC_METHOD(delay1);
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           SC_METHOD(delay2);
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           SC_METHOD(delay3);
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        }
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        virtual ~scIF();
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private:
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        uint32_t m_nPC;
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        uint32_t m_nIR;
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private:
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        bool   m_b_flush;
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        bool   m_b_start;
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    sc_event trigger;
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        sc_event trigger1_if,trigger2_if,trigger3_if;
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private:
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        uint32_t  read_mem_data(uint32_t);
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        void entry(void);
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};

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