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[/] [scarm/] [trunk/] [src/] [scMEM.cpp] - Blame information for rev 10

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// scMEM.cpp: implementation of the scMEM class.
/*                            -------------------
    begin                : Oct 2 2002
    copyright            : (C) 2002 UESTC
    author               : Zhong Tao
    email                : zhong@opencores.org
 ***************************************************************************/
 
/***************************************************************************
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 ***************************************************************************/
#include "scMEM.h"
#include "scRAM.h"
#include "global.h"
#define DEBUG
 
//////////////////////////////////////////////////////////////////////
// Construction/Destruction
//////////////////////////////////////////////////////////////////////
 
scMEM::scMEM(sc_module_name name_):sc_module(name_)
{
        m_interrupt=0;
        m_b_is_mrt=0;
 
    SC_METHOD(entry);
        sensitive_pos<<in_b_Clock;
        SC_METHOD(delta_delay1);
        SC_METHOD(write_mem);
}
 
scMEM::~scMEM()
{
 
}
 
void scMEM::entry()
{
 
 m_Rd=in_Rd;
 m_n_Rd=in_n_Rd;
 m_Rn=in_Rn;
 m_b_W_Rd=in_b_write_Rd;
 m_b_WB=in_b_WB;
 m_n_Result=in_n_Result;
 m_b_excute=in_b_excute;
 m_b_ls=in_b_ls;
 m_b_Load=in_b_Load;
 m_b_is_mrt=in_is_mrt;
 
 
if((m_b_excute)||(m_Rd==R_PC))
{
 
  if(m_Rd==R_PC)
  {
          if((m_b_excute)){
            //cout<<"BRANCHXXXXXXXXXXXXXX"<<endl;
 
            m_b_W_Rd=false;
        m_b_WB=false;
 
                m_n_Result=in_n_Result;
 
                //cout<<"mem  excute b="<<in_n_Result<<endl;
          }
           else
           {
                  // cout<<"mem dont exc b="<<in_n_Result<<endl;
              m_b_WB=false;
                  m_b_W_Rd=false;
              m_n_Result=in_n_Result;
 
           }
 
            m_b_excute=0;
                m_b_W_Rd=0;
                //out_n_Rn=in_n_Result;//change base address
 
  }else
  {
 
            if(m_b_ls==true)
                {
 
                        cout<<"addr="<<in_n_Result<<endl;
                        if(m_b_is_mrt==0)
                        {
                if(in_b_Pre==1)
                                {
 
                   //   m_b_WB=in_b_WB;  
                                    if(m_b_WB==1)
 
                                                m_n_Rn=m_n_Result;
                                        else
                                                m_n_Rn=m_n_Rn;
 
                     m_n_Addr=m_n_Result;
                                        //cout<<"m_n_Rn="<<m_n_Rn<<endl;
 
 
 
                                }else
                                {
                                        m_b_WB=1;
                                        /*
                                    if(m_b_WB==1)
                                                m_n_Rn=m_n_Result;
                                        else
                                                m_n_Rn=m_n_Rn;
                                                */
                                        //add to Rn after transfer
                       //always
                                        m_n_Addr=m_n_Rn;// post
 
                                        m_n_Rn=m_n_Result;
 
                        //cout<<"after"<<endl;                          
                                }
               //read meory
                                if(m_b_Load==1)
                                {
 
                                        out_n_Addr=m_n_Addr;//pre
                                }else
                                {
                                    out_n_Addr=m_n_Addr;
                           //write memory
                                inout_n_Data=m_n_Rd;
                                }
                        }else
                        {
                             out_n_Addr=m_n_Result;
 
                        }
 
 
                  //    cout<<"ex out"<<in_n_Result<<endl;
 
                }else///load/store
                {
                   m_n_Result=in_n_Result;
                    m_b_W_Rd=in_b_write_Rd;
                   m_n_Rn=in_n_Rn;
 
                   m_b_W_Rd=(m_b_W_Rd)&&(m_b_excute);
 
                }
 
  }//if Branch
 
}//if excute 
else
{
  m_b_W_Rd=false;
  m_b_WB=false;
}
 trigger.notify(SC_ZERO_TIME);
}
 
void scMEM::dump(uint32_t addr)
{
 
}
 
 
void scMEM::delta_delay1()
{
        next_trigger(trigger);
/*
    if(m_interrupt==1)
  {
 
                m_b_excute=0;
    g_interrupt=1;
        g_count++;
        if(g_count>1) sc_stop();
  }else
  {
    g_interrupt=0;
  }
  */
        //transfer data between memory and register
 
                if((m_b_Load==1)&&(m_b_ls==1))
                        {
                            //read from memory;
                            m_b_W_Rd=(m_b_W_Rd)&&(m_b_excute);
                                out_n_Addr=m_n_Addr;
                                m_n_Result=inout_n_Data;
 
 
                }else
                if((m_b_Load==0)&&(m_b_ls==1))
                {
 
                //store data
 
                    out_n_Addr_reg=m_Rd;
                    m_n_Rd=inout_n_Data_reg;
                        //cout<<"r"<<m_Rd<<"="<<m_n_Rd<<endl;
                        //cout<<"store "<<endl;
                        //out_b_nRW=1;
                        out_n_Addr=m_n_Addr;
                        inout_n_Data=m_n_Rd;
                        //cout<<"store r"<<m_Rd<<":"<<m_n_Rd<<" to "<<m_n_Result<<endl;
                 m_b_W_Rd=0;
                         //m_b_WB=1;
 
                                //write to memory;
                        trigger_mem.notify(SC_ZERO_TIME);
                }else
                {
 
                }
 
                /*
                        if(m_interrupt==1)
                        {
 
                                if(m_n_Addr=0xec0)m_n_Result=0x40000000;
                                if(m_n_Addr=0xec4)m_n_Result=0x70000000;
                                if(m_n_Addr=0xec8)m_n_Result=0x80000000;
                                if(m_n_Addr=0xecc)m_n_Result=0x70000000;
                        }
                        */
 out_Rd=m_Rd;
 //cout<<"mem Rd: r"<<m_Rd<<"="<<m_n_Result<<endl;
 
 out_Rn=m_Rn;
 out_n_Rn=m_n_Rn;
 out_b_W_Rd=(m_b_W_Rd)&&m_b_excute;
 //cout<<"ddd"<<m_b_W_Rd<<endl;
 out_b_WB=m_b_WB&&m_b_excute;
 out_n_Result=m_n_Result;
 out_b_excute=m_b_excute;
 
 
}
 
void scMEM::write_mem()
{
        next_trigger(trigger_mem);
    out_b_nRW=1;
        out_n_Addr=m_n_Result;
    inout_n_Data=m_n_Rd;//write to memory;
 
    //cout<<"write to mem:"<<m_n_Result<<endl;
        //out_n_Addr=m_n_Result;
        //uint32_t temp=inout_n_Data;
        //cout<<"  read from mem"<<temp<<endl;
        //cout<<"mem write reg="<<endl;
}

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[/] [scarm/] [trunk/] [src/] [scMEM.cpp] - Blame information for rev 10

Line No.	Rev	Author	Line
1	5	zhong	`// scMEM.cpp: implementation of the scMEM class.`
2			`/* -------------------`
3			`begin : Oct 2 2002`
4			`copyright : (C) 2002 UESTC`
5			`author : Zhong Tao`
6			`email : zhong@opencores.org`
7			`***************************************************************************/`
8
9			`/***************************************************************************`
10			`* *`
11			`* This program is free software; you can redistribute it and/or modify *`
12			`* it under the terms of the GNU General Public License as published by *`
13			`* the Free Software Foundation; either version 2 of the License, or *`
14			`* (at your option) any later version. *`
15			`* *`
16			`***************************************************************************/`
17			`#include "scMEM.h"`
18			`#include "scRAM.h"`
19			`#include "global.h"`
20			`#define DEBUG`
21
22			`//////////////////////////////////////////////////////////////////////`
23			`// Construction/Destruction`
24			`//////////////////////////////////////////////////////////////////////`
25
26			`scMEM::scMEM(sc_module_name name_):sc_module(name_)`
27			`{`
28			`m_interrupt=0;`
29			`m_b_is_mrt=0;`
30
31			`SC_METHOD(entry);`
32			`sensitive_pos<<in_b_Clock;`
33			`SC_METHOD(delta_delay1);`
34			`SC_METHOD(write_mem);`
35			`}`
36
37			`scMEM::~scMEM()`
38			`{`
39
40			`}`
41
42			`void scMEM::entry()`
43			`{`
44
45			`m_Rd=in_Rd;`
46			`m_n_Rd=in_n_Rd;`
47			`m_Rn=in_Rn;`
48			`m_b_W_Rd=in_b_write_Rd;`
49			`m_b_WB=in_b_WB;`
50			`m_n_Result=in_n_Result;`
51			`m_b_excute=in_b_excute;`
52			`m_b_ls=in_b_ls;`
53			`m_b_Load=in_b_Load;`
54			`m_b_is_mrt=in_is_mrt;`
55
56
57			`if((m_b_excute)\|\|(m_Rd==R_PC))`
58			`{`
59
60			`if(m_Rd==R_PC)`
61			`{`
62			`if((m_b_excute)){`
63			`//cout<<"BRANCHXXXXXXXXXXXXXX"<<endl;`
64
65			`m_b_W_Rd=false;`
66			`m_b_WB=false;`
67
68			`m_n_Result=in_n_Result;`
69
70			`//cout<<"mem excute b="<<in_n_Result<<endl;`
71			`}`
72			`else`
73			`{`
74			`// cout<<"mem dont exc b="<<in_n_Result<<endl;`
75			`m_b_WB=false;`
76			`m_b_W_Rd=false;`
77			`m_n_Result=in_n_Result;`
78
79			`}`
80
81			`m_b_excute=0;`
82			`m_b_W_Rd=0;`
83			`//out_n_Rn=in_n_Result;//change base address`
84
85			`}else`
86			`{`
87
88			`if(m_b_ls==true)`
89			`{`
90
91			`cout<<"addr="<<in_n_Result<<endl;`
92			`if(m_b_is_mrt==0)`
93			`{`
94			`if(in_b_Pre==1)`
95			`{`
96
97			`// m_b_WB=in_b_WB;`
98			`if(m_b_WB==1)`
99
100			`m_n_Rn=m_n_Result;`
101			`else`
102			`m_n_Rn=m_n_Rn;`
103
104			`m_n_Addr=m_n_Result;`
105			`//cout<<"m_n_Rn="<<m_n_Rn<<endl;`
106
107
108
109			`}else`
110			`{`
111			`m_b_WB=1;`
112			`/*`
113			`if(m_b_WB==1)`
114			`m_n_Rn=m_n_Result;`
115			`else`
116			`m_n_Rn=m_n_Rn;`
117			`*/`
118			`//add to Rn after transfer`
119			`//always`
120			`m_n_Addr=m_n_Rn;// post`
121
122			`m_n_Rn=m_n_Result;`
123
124			`//cout<<"after"<<endl;`
125			`}`
126			`//read meory`
127			`if(m_b_Load==1)`
128			`{`
129
130			`out_n_Addr=m_n_Addr;//pre`
131			`}else`
132			`{`
133			`out_n_Addr=m_n_Addr;`
134			`//write memory`
135			`inout_n_Data=m_n_Rd;`
136			`}`
137			`}else`
138			`{`
139			`out_n_Addr=m_n_Result;`
140
141			`}`
142
143
144			`// cout<<"ex out"<<in_n_Result<<endl;`
145
146			`}else///load/store`
147			`{`
148			`m_n_Result=in_n_Result;`
149			`m_b_W_Rd=in_b_write_Rd;`
150			`m_n_Rn=in_n_Rn;`
151
152			`m_b_W_Rd=(m_b_W_Rd)&&(m_b_excute);`
153
154			`}`
155
156			`}//if Branch`
157
158			`}//if excute`
159			`else`
160			`{`
161			`m_b_W_Rd=false;`
162			`m_b_WB=false;`
163			`}`
164			`trigger.notify(SC_ZERO_TIME);`
165			`}`
166
167			`void scMEM::dump(uint32_t addr)`
168			`{`
169
170			`}`
171
172
173			`void scMEM::delta_delay1()`
174			`{`
175			`next_trigger(trigger);`
176			`/*`
177			`if(m_interrupt==1)`
178			`{`
179
180			`m_b_excute=0;`
181			`g_interrupt=1;`
182			`g_count++;`
183			`if(g_count>1) sc_stop();`
184			`}else`
185			`{`
186			`g_interrupt=0;`
187			`}`
188			`*/`
189			`//transfer data between memory and register`
190
191			`if((m_b_Load==1)&&(m_b_ls==1))`
192			`{`
193			`//read from memory;`
194			`m_b_W_Rd=(m_b_W_Rd)&&(m_b_excute);`
195			`out_n_Addr=m_n_Addr;`
196			`m_n_Result=inout_n_Data;`
197
198
199			`}else`
200			`if((m_b_Load==0)&&(m_b_ls==1))`
201			`{`
202
203			`//store data`
204
205			`out_n_Addr_reg=m_Rd;`
206			`m_n_Rd=inout_n_Data_reg;`
207			`//cout<<"r"<<m_Rd<<"="<<m_n_Rd<<endl;`
208			`//cout<<"store "<<endl;`
209			`//out_b_nRW=1;`
210			`out_n_Addr=m_n_Addr;`
211			`inout_n_Data=m_n_Rd;`
212			`//cout<<"store r"<<m_Rd<<":"<<m_n_Rd<<" to "<<m_n_Result<<endl;`
213			`m_b_W_Rd=0;`
214			`//m_b_WB=1;`
215
216			`//write to memory;`
217			`trigger_mem.notify(SC_ZERO_TIME);`
218			`}else`
219			`{`
220
221			`}`
222
223			`/*`
224			`if(m_interrupt==1)`
225			`{`
226
227			`if(m_n_Addr=0xec0)m_n_Result=0x40000000;`
228			`if(m_n_Addr=0xec4)m_n_Result=0x70000000;`
229			`if(m_n_Addr=0xec8)m_n_Result=0x80000000;`
230			`if(m_n_Addr=0xecc)m_n_Result=0x70000000;`
231			`}`
232			`*/`
233			`out_Rd=m_Rd;`
234			`//cout<<"mem Rd: r"<<m_Rd<<"="<<m_n_Result<<endl;`
235
236			`out_Rn=m_Rn;`
237			`out_n_Rn=m_n_Rn;`
238			`out_b_W_Rd=(m_b_W_Rd)&&m_b_excute;`
239			`//cout<<"ddd"<<m_b_W_Rd<<endl;`
240			`out_b_WB=m_b_WB&&m_b_excute;`
241			`out_n_Result=m_n_Result;`
242			`out_b_excute=m_b_excute;`
243
244
245			`}`
246
247			`void scMEM::write_mem()`
248			`{`
249			`next_trigger(trigger_mem);`
250			`out_b_nRW=1;`
251			`out_n_Addr=m_n_Result;`
252			`inout_n_Data=m_n_Rd;//write to memory;`
253
254			`//cout<<"write to mem:"<<m_n_Result<<endl;`
255			`//out_n_Addr=m_n_Result;`
256			`//uint32_t temp=inout_n_Data;`
257			`//cout<<" read from mem"<<temp<<endl;`
258			`//cout<<"mem write reg="<<endl;`
259			`}`