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[/] [scarm/] [trunk/] [src/] [scMEM.h] - Blame information for rev 8

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1 5 zhong
// scMEM.h: interface for the scMEM class.
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/*                            -------------------
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    begin                : Oct 2 2002
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    copyright            : (C) 2002 UESTC
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    author               : Zhong Tao
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    email                : zhong@opencores.org
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 ***************************************************************************/
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/***************************************************************************
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 *                                                                         *
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 *   This program is free software; you can redistribute it and/or modify  *
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 *   it under the terms of the GNU General Public License as published by  *
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 *   the Free Software Foundation; either version 2 of the License, or     *
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 *   (at your option) any later version.                                   *
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 *                                                                         *
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 ***************************************************************************/
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#if !defined(AFX_SCMEM_H__D38D2414_AB4A_11D6_BB1E_000000000000__INCLUDED_)
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#define AFX_SCMEM_H__D38D2414_AB4A_11D6_BB1E_000000000000__INCLUDED_
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#if _MSC_VER > 1000
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#pragma once
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#endif // _MSC_VER > 1000
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#include <systemc.h>
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#include "scTypes.h"
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#include "scRegisterFile.h"
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class scMEM : public sc_module
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{
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        public:
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        sc_in<bool> in_b_Clock;
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        sc_in<bool> in_interrupt;
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        sc_in<bool> in_b_branch_taken;
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    sc_in<bool> in_b_excute;
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        sc_out<bool> out_b_excute;
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        //sc_out<bool> out_b_flush;
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        //access memory
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        sc_outmaster<bool>  out_b_nRW;
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        sc_outmaster<uint32_t> out_n_Addr;//  address bus
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        sc_inoutslave<uint32_t>  inout_n_Data; //Instruction bus
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        //access regs
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        sc_outmaster<bool>  out_b_nRW_reg;
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        sc_outmaster<REGS> out_n_Addr_reg;//  address bus
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        sc_inoutslave<uint32_t>  inout_n_Data_reg; //Instruction bus
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        //EX to MEM
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        sc_in<REGS>   in_Rd;
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        sc_in<bool>   in_b_write_Rd;
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        sc_in<REGS>   in_Rn;    //Reg
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        sc_in<uint32_t> in_n_Rn;//data
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        sc_in<bool>   in_b_ls;
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        sc_in<bool>   in_is_mrt;
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    sc_in<bool>   in_b_Pre;// alter base reg before?
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    sc_in<bool>  in_b_Load;// load or store
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    sc_in<bool>  in_b_WB;  //if i should write back to base reg?
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        sc_in<uint32_t> in_n_Result;//result
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        sc_in<uint32_t> in_n_Rd;//write to memory from source Rd
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        //MEM to WB
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        sc_out<bool>         out_b_W_Rd;
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        sc_out<bool>         out_b_WB;
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        sc_out<REGS>         out_Rd;//target
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        sc_out<uint32_t>     out_n_Result;
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        sc_out<REGS>         out_Rn;//write-back register
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        sc_out<uint32_t>     out_n_Rn; //write-back data  
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public:
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        void write_mem();
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        void delta_delay1();
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        void dump(uint32_t);
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        void entry();
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        SC_HAS_PROCESS(scMEM);
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        scMEM(sc_module_name);
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        virtual ~scMEM();
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private:
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   sc_event trigger,trigger_mem;
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 REGS m_Rd;
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 REGS m_Rn;
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 bool m_b_W_Rd,m_b_WB,m_interrupt,m_b_is_mrt;
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 uint32_t m_n_Result,m_n_Rn,m_n_Rd,m_n_Addr;
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 bool m_b_excute,m_b_ls,m_b_Load;
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};
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#endif // !defined(AFX_SCMEM_H__D38D2414_AB4A_11D6_BB1E_000000000000__INCLUDED_)

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