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[/] [scarm/] [trunk/] [src/] [scRegisterFile.cpp] - Blame information for rev 10

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1 5 zhong
// scRegisterFile.cpp: implementation of the scRegisterFile class.
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/*                            -------------------
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    begin                : Oct 2 2002
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    copyright            : (C) 2002 UESTC
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    author               : Zhong Tao
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    email                : zhong@opencores.org
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 ***************************************************************************/
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/***************************************************************************
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 *                                                                         *
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 *   This program is free software; you can redistribute it and/or modify  *
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 *   it under the terms of the GNU General Public License as published by  *
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 *   the Free Software Foundation; either version 2 of the License, or     *
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 *   (at your option) any later version.                                   *
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 *                                                                         *
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 ***************************************************************************/
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#include "scRegisterFile.h"
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#define DEBUG
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//////////////////////////////////////////////////////////////////////
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// Construction/Destruction
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//////////////////////////////////////////////////////////////////////
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scRegisterFile::~scRegisterFile()
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{
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}
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void scRegisterFile::set_mode(enum MODE m)
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{
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        m_Mode=m;
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        r[0]=&m_r0;
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    r[1]=&m_r1;
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        r[2]=&m_r2;
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        r[3]=&m_r3;
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        r[4]=&m_r4;
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        r[5]=&m_r5;
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        r[6]=&m_r6;
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        r[7]=&m_r7;
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        r[8]=&m_r8;
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        r[9]=&m_r9;
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        r[10]=&m_r10;
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        r[11]=&m_r11;
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        r[12]=&m_r12;
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        r[13]=&m_r13;
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        r[14]=&m_r14;
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        r[15]=&m_r15;
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        r[16]=&m_cpsr;
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        r[17]=&m_spsr;
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switch(m_Mode)
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{
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case M_USER:
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        {
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                //16 general register   
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          //printf("M_USER Mode \n");   
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          break;
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    }
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case M_FIQ://7 reg for FIQ mode 
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        {
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        r[8]=&m_r8_fiq;
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        r[9]=&m_r9_fiq;
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        r[10]=&m_r10_fiq;
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        r[11]=&m_r11_fiq;
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        r[12]=&m_r12_fiq;
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        r[13]=&m_r13_fiq;
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        r[14]=&m_r14_fiq;
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        r[17]=&m_spsr_fiq;
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        printf("M_FIQ\n");
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        break;
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        }
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case M_SVC : //2 reg for supervisor mode
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        {
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        r[13]=&m_r13_svc;
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        r[14]=&m_r14_svc;
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        //r[17]=&m_spsr_svc;
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        m_spsr_svc=m_cpsr;
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        break;
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        }
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case M_ABORT://2 reg for abort mode
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        {
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        r[13]=&m_r13_abt;
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        r[14]=&m_r14_abt;
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        r[17]=&m_spsr_abt;
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        break;
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        }
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case M_IRQ://2 m_reg for IRQ mode
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        {
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                r[13]=&m_r13_irq;
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                r[14]=&m_r14_irq;
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                r[17]=&m_spsr_irq;
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                break;
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        }
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case M_UNDEF://2 m_reg undefined instruction mode
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        {
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        r[13]=&m_r13_und;
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        r[14]=&m_r14_und;
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        r[17]=&m_spsr_und;
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        break;
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        }
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default:
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        {
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      cout<<"error in Regsiger File"<<endl;
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        }
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}//end of switch (m_Mode)
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}
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void scRegisterFile::entry()
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{
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        uint32_t i=in_REG;
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        #if defined(DEBUG)
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        if(i>0x11) {
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         cout<<" error00:try to access register which doesn't exist. "<<endl;
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         sc_stop();
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        }
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#endif
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        if(m_rw==0)
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    {
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                inout_n_Data=*(r[i]);
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         //cout<<"read port0:"<<"r"<<hex<<i<<"="<<inout_n_Data<<endl;
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        }else
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        {       //cout<<"port0:"<<"r"<<hex<<i<<"="<<inout_n_Data<<endl;
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                (*r[i])=inout_n_Data;
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        m_rw=0;
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        }
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}
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void scRegisterFile::change_mode()
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{
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   MODE temp;
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   temp=in_MODE;
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   set_mode(temp);
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}
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void scRegisterFile::entry1()
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{
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        uint32_t i=in_REG1;
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        #if defined(DEBUG)
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        if(i>0x11) {
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                cout<<" error01:try to access register which doesn't exist. "<<endl;
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         sc_stop();
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        }
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#endif
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        if(m_rw==0)
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    {
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                inout_n_Data1=(*r[i]);
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        }else
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        {
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                (*r[i])=inout_n_Data1;
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        //      cout<<"port1:"<<"r"<<hex<<i<<"="<<inout_n_Data1<<endl;
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            m_rw=0;
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        }
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}
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void scRegisterFile::entry2()
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{
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        uint32_t i=in_REG2;
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        #if defined(DEBUG)
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        if(i>0x11) {
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         cout<<" error02:try to access register which doesn't exist. "<<endl;
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         sc_stop();
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        }
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#endif
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        if(m_rw==0)
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    {
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                inout_n_Data2=*r[i];
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        //      cout<<(*r[15])<<"read reg"<<endl;
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        }else
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        {
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                (*r[i])=inout_n_Data2;
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        //      cout<<"port2:"<<"r"<<hex<<i<<"="<<inout_n_Data2<<endl;
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                m_rw=0;
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        }
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}
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void scRegisterFile::entry4()
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{
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        uint32_t i=in_REG_PC;
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#if defined(DEBUG)
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        if(i>0x11) {
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         cout<<" error04:try to access register which doesn't exist. "<<endl;
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         sc_stop();
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        }
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#endif
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        if(m_rw==0)
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    {
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                inout_n_Data_PC=*r[i];
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        }else
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        {
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                *r[i]=inout_n_Data_PC;
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                //      cout<<"port pc:"<<hex<<(*r[15])<<"="<<hex<<inout_n_Data_PC<<endl;
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                m_rw=0;
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        }
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}
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void scRegisterFile::display()
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{
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  cout<<"                 PC:"<<hex<<m_r15;
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  cout<<"   CPSR:";//0100
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  // Bit masks for CPSR
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    if((m_cpsr&N_FLAG)==N_FLAG) cout<<"N";else cout<<"n";
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    if((m_cpsr&Z_FLAG)==Z_FLAG) cout<<"Z"; else cout<<"z";
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    if((m_cpsr&C_FLAG)==C_FLAG) cout<<"C"; else cout<<"c";
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    if((m_cpsr&V_FLAG)==V_FLAG) cout<<"V"; else cout<<"v"<<endl;
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  cout<<"                r0="<<hex<<m_r0;
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  cout<<" r1="<<hex<<m_r1;
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  cout<<" r2="<<hex<<m_r2;
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  cout<<" r3="<<hex<<m_r3;
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  cout<<" r4="<<hex<<m_r4;
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  cout<<" r5="<<hex<<m_r5;
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  cout<<" r6="<<hex<<m_r6;
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  cout<<" r7="<<hex<<m_r7<<endl;
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  cout<<"                r8="<<hex<<m_r8;
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  cout<<" r9="<<hex<<m_r9;
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  cout<<" r10="<<hex<<m_r10;
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  cout<<" r11="<<hex<<m_r11;
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  cout<<" r12="<<hex<<m_r12;
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  cout<<" r13="<<hex<<m_r13;
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  cout<<"link="<<hex<<m_r14<<endl<<endl;
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}
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void scRegisterFile::rw()
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{
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       m_rw=1;
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}
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void scRegisterFile::rw1()
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{
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       m_rw=1;
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}
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void scRegisterFile::rw2()
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{
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       m_rw=1;
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}
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void scRegisterFile::rw4()
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{
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       m_rw=1;
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}
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void scRegisterFile::show()
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{
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}

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