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[/] [scarm/] [trunk/] [src/] [scSW1.cpp] - Blame information for rev 10

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Line No. Rev Author Line
1 5 zhong
///////////////////////////////////////////////////////////////////////////////
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// This program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public License
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// as published by the Free Software Foundation; either version 2
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// of the License, or (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
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//////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////              
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//          
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//  Original Author: Allen Tao Zhong,
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//  University of Electronic Science and Technology in China
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//  email: zhong@opencores.org
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//  info   This is a SystemC ARM model
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// scSW1.cpp: implementation of the scSW1 class.
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//
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//////////////////////////////////////////////////////////////////////
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#include "scSW1.h"
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//////////////////////////////////////////////////////////////////////
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// Construction/Destruction
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//////////////////////////////////////////////////////////////////////
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scSW1::scSW1(uint32_t i)
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{
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        ir.imm=i;
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        ir.rd=i>>12;
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        ir.rn=i>>16;
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    ir.ls=i>>20;
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        ir.wb=i>>21;
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  ir.b=i>>22;
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  ir.u=i>>23;
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  ir.p=i>>24;
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  ir.hash=i>>25;
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  ir.pad=i>>26;
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  ir.cond=i>>28;
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}
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scSW1::~scSW1()
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{
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}
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const char* scSW1::kind_string_l = "LDR";
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const char* scSW1::kind_string_s = "STR";
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const char* scSW1::kind()
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{
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        if(ir.ls)
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         return kind_string_l;
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        else
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                 return kind_string_s;
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}
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uint32_t scSW1::A()
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{
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   return ir.rn;
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}
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REGS scSW1::Rd()
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{
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 return REGS(ir.rd);
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}
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uint32_t scSW1::B()
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{
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   return ir.imm;
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}
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bool scSW1::is_imm()
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{
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 return true;
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}
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OPCODE scSW1::op()
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{
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   if(ir.u==0)
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        return OP_SUB;
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   else
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        return OP_ADD;
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}
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COND scSW1::cond()
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{
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  return COND(ir.cond);
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}
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SHIFT scSW1::shift_type()
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{
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 return SHIFT(0);
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}
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uint32_t scSW1::dist()
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{
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 return 0;
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}
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bool scSW1::is_shift()
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{
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  return false;
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}
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bool scSW1::pre()
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{
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 return ir.p;
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}
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bool scSW1::load()
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{
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 return ir.ls;
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}
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bool scSW1::wb()
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{
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  return ir.wb;
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}
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REGS scSW1::Rn()
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{
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  return REGS(ir.rn);
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}
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bool scSW1::is_mult()
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{
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  return false;
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}
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bool scSW1::is_ls()
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{
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  return true;
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}
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bool scSW1::is_rs()
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{
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  return false;
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}
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bool scSW1::is_branch()
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{
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 return false;
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}
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bool scSW1::set()
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{
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 return false;
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}

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