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[/] [scarm/] [trunk/] [src/] [scSW2.cpp] - Blame information for rev 8

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Line No. Rev Author Line
1 5 zhong
// scSW2.cpp: implementation of the scSW1 class.
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/*                            -------------------
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    begin                : Oct 2 2002
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    copyright            : (C) 2002 UESTC
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    author               : Zhong Tao
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    email                : zhong@opencores.org
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 ***************************************************************************/
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/***************************************************************************
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 *                                                                         *
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 *   This program is free software; you can redistribute it and/or modify  *
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 *   it under the terms of the GNU General Public License as published by  *
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 *   the Free Software Foundation; either version 2 of the License, or     *
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 *   (at your option) any later version.                                   *
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 *                                                                         *
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 ***************************************************************************/
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#include "scSW2.h"
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//////////////////////////////////////////////////////////////////////
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// Construction/Destruction
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//////////////////////////////////////////////////////////////////////
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scSW2::scSW2(uint32_t i)
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{
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  ir.rm=i;
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  ir.pad2=i>>4;
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  ir.type=i>>5;
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  ir.shift=i>>7;
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  ir.rd=i>>12;
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  ir.rn=i>>16;
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  ir.ls=i>>20;
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  ir.wb=i>>21;
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  ir.b=i>>22;
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  ir.u=i>>23;
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  ir.p=i>>24;
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  ir.hash=i>>25;
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  ir.pad=i>>26;
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  ir.cond=i>>28;
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}
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scSW2::~scSW2()
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{
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}
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const char* scSW2::kind_string_l = "LDR";
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const char* scSW2::kind_string_s = "STR";
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const char* scSW2::kind()
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{
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        if(ir.ls)
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         return kind_string_l;
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        else
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                 return kind_string_s;
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}
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uint32_t scSW2::A()
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{
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  return ir.rn;
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}
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REGS scSW2::Rd()
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{
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 return REGS(ir.rd);
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}
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bool scSW2::is_imm()
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{
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 return ir.hash;
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}
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uint32_t scSW2::B()
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{
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  return ir.rm;
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}
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SHIFT scSW2::shift_type()
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{
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  return SHIFT(ir.type);
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}
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COND scSW2::cond()
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{
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  return COND(ir.cond);
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}
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bool scSW2::is_shift()
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{
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  return true;
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}
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bool scSW2::is_rs()
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{
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  return true;
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}
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uint32_t scSW2::dist()
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{
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  return ir.shift;
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}
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bool scSW2::pre()
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{
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 return ir.p;
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}
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bool scSW2::wb()
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{
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 return ir.wb;
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}
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bool scSW2::load()
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{
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  return ir.ls;
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}
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REGS scSW2::Rn()
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{
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 return REGS(ir.rn);
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}
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bool scSW2::is_ls()
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{
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  return true;
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}
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bool scSW2::is_word()
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{
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  return !(ir.b);//byte or word
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}
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OPCODE scSW2::op()
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{
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        if(ir.u==0)
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        {
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        return OP_SUB;
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        }else
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                return OP_ADD;
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}
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bool scSW2::is_branch()
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{
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  return false;
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}
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bool scSW2::is_mult()
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{
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  return false;
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}
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bool scSW2::set()
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{
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  return false;
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}

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