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[/] [scarm/] [trunk/] [src/] [scWB.cpp] - Blame information for rev 10

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Line No. Rev Author Line
1 5 zhong
// scWB.cpp: implementation of the scWB class.
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/*                            -------------------
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    begin                : Oct 2 2002
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    copyright            : (C) 2002 UESTC
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    author               : Zhong Tao
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    email                : zhong@opencores.org
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 ***************************************************************************/
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/***************************************************************************
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 *                                                                         *
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 *   This program is free software; you can redistribute it and/or modify  *
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 *   it under the terms of the GNU General Public License as published by  *
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 *   the Free Software Foundation; either version 2 of the License, or     *
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 *   (at your option) any later version.                                   *
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 *                                                                         *
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 ***************************************************************************/
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#include "scWB.h"
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//#define DEBUG
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//////////////////////////////////////////////////////////////////////
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// Construction/Destruction
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//////////////////////////////////////////////////////////////////////
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scWB::scWB(sc_module_name name_):sc_module(name_)
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{
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        m_Rn=REGS(13);
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        m_Rd=REGS(13);
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        m_n_Rn=0;
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        m_n_Rd=0;
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        m_b_excute=false;
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        m_b_write=false;
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        m_b_wb=false;
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    SC_METHOD(entry);
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        sensitive_pos<<in_b_Clock;
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        SC_METHOD(out_delay);
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        SC_METHOD(delay1);
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}
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scWB::~scWB()
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{
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}
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void scWB::entry()
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{
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        m_Rd=in_Rd;
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        m_Rn=in_Rn;
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        m_n_Rd=in_n_Result;
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        m_n_Rn=in_n_Rn;
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    m_b_excute=in_b_excute;
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        m_b_write=in_b_W_Rd;
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        m_b_wb=in_b_WB;
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if(m_b_excute)
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{
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  if((m_Rd!=R_PC)&&m_b_write)
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  {
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    inout_n_Data1=m_n_Rd;
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  }
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     if(m_b_wb)//write back
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  {
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    inout_n_Data2=m_n_Rn;
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  }
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  //regs();
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}//if excute
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trigger_wb1.notify(SC_ZERO_TIME);
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}
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void scWB::regs()
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{
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                //read CPSR
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      uint32_t R=0;
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                //      out_b_RW=0;
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                out_REG1=R_PC;
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                R=inout_n_Data1;
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          cout<<"       PC:"<<R;//0100
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                //out_b_RW=0;
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                out_REG1=R_CPSR;
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                R=inout_n_Data1;
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          cout<<" CPSR:";//0100
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  // Bit masks for CPSR
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    if((R&N_FLAG)==N_FLAG) cout<<"N";else cout<<"n";
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    if((R&Z_FLAG)==Z_FLAG) cout<<"Z"; else cout<<"z";
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    if((R&C_FLAG)==C_FLAG) cout<<"C"; else cout<<"c";
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    if((R&V_FLAG)==V_FLAG) cout<<"V"; else cout<<"v";
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        cout<<"  "<<endl;
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        //cout<<"WB"<<endl;
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         cout<<"        ";
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                for(int i=0;i<15;i++)
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                {
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                     //out_b_RW1=0;
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                     out_REG1=REGS(i);
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                     R=inout_n_Data1;
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                         cout<<"r"<<i<<"="<<R<<" ";
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                         if((i==4)||(i==9)) cout<<endl<<"       ";
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                }
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                cout<<endl;
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}
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void scWB::out_delay()
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{
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  next_trigger(trigger_wb1);
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  if(m_b_excute)
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{
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   if((m_Rd!=R_PC)&&m_b_write)
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   {
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      //cout<<"R"<<m_Rd<<"="<<m_n_Rd<<endl;
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          out_b_RW1=1;
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      out_REG1=m_Rd;
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          inout_n_Data1=m_n_Rd;
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   }
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     if(m_b_wb)//write back
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  {
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       out_b_RW2=1;
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           out_REG2=m_Rn;
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           //cout<<"m_n_Rn="<<m_n_Rn<<endl;
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       inout_n_Data2=m_n_Rn;
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         }
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}
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 //regs();
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  //trigger_wb2.notify(SC_ZERO_TIME);
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}
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void scWB::delay1()
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{
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  next_trigger(trigger_wb2);
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         out_REG2=REGS(0);
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  uint32_t temp=inout_n_Data2;
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  cout<<"       wb r0="<<temp;
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    out_REG2=REGS(1);
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   temp=inout_n_Data2;
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  cout<<" wb r1="<<temp;
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      out_REG2=REGS(2);
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   temp=inout_n_Data2;
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  cout<<" wb r2="<<temp;
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    out_REG2=REGS(3);
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   temp=inout_n_Data2;
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  cout<<" wb r3="<<temp<<endl;
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}

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