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[/] [scarm/] [trunk/] [src/] [scWB.h] - Blame information for rev 8
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// scWB.h: interface for the scWB class.
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/* -------------------
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begin : Oct 2 2002
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copyright : (C) 2002 UESTC
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author : Zhong Tao
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email : zhong@opencores.org
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***************************************************************************/
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/***************************************************************************
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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***************************************************************************/
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#if !defined(AFX_SCWB_H__D38D2415_AB4A_11D6_BB1E_000000000000__INCLUDED_)
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#define AFX_SCWB_H__D38D2415_AB4A_11D6_BB1E_000000000000__INCLUDED_
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#if _MSC_VER > 1000
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#pragma once
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#endif // _MSC_VER > 1000
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#include <systemc.h>
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#include "scRegisterFile.h"
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class scWB : public sc_module
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{
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public:
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sc_in<bool> in_b_Clock;
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sc_in<bool> in_b_excute;
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sc_in<REGS> in_Rd;
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sc_in<uint32_t> in_n_Result;
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sc_in<REGS> in_Rn;
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sc_in<uint32_t> in_n_Rn;
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sc_in<bool> in_b_W_Rd;//if write Rd?
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sc_in<bool> in_b_WB;
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//regs
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sc_outmaster <bool> out_b_RW1;// 0-Read 1-Write
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sc_outmaster<REGS> out_REG1;
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sc_inoutslave<uint32_t> inout_n_Data1;
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sc_outmaster <bool> out_b_RW2;// 0-Read 1-Write
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sc_outmaster<REGS> out_REG2;
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sc_inoutslave<uint32_t> inout_n_Data2;
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public:
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void delay1();
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void out_delay();
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void regs();
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void entry();
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SC_HAS_PROCESS(scWB);
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scWB(sc_module_name);
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virtual ~scWB();
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private:
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sc_event trigger_wb1,trigger_wb2;
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REGS m_Rn;
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REGS m_Rd;
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uint32_t m_n_Rn;
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uint32_t m_n_Rd;
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bool m_b_excute;
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bool m_b_write;
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bool m_b_wb;
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};
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#endif // !defined(AFX_SCWB_H__D38D2415_AB4A_11D6_BB1E_000000000000__INCLUDED_)
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