OpenCores
URL https://opencores.org/ocsvn/scarm/scarm/trunk

Subversion Repositories scarm

[/] [scarm/] [trunk/] [src/] [scWB.h] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 zhong
// scWB.h: interface for the scWB class.
2
/*                            -------------------
3
    begin                : Oct 2 2002
4
    copyright            : (C) 2002 UESTC
5
    author               : Zhong Tao
6
    email                : zhong@opencores.org
7
 ***************************************************************************/
8
 
9
/***************************************************************************
10
 *                                                                         *
11
 *   This program is free software; you can redistribute it and/or modify  *
12
 *   it under the terms of the GNU General Public License as published by  *
13
 *   the Free Software Foundation; either version 2 of the License, or     *
14
 *   (at your option) any later version.                                   *
15
 *                                                                         *
16
 ***************************************************************************/
17
#if !defined(AFX_SCWB_H__D38D2415_AB4A_11D6_BB1E_000000000000__INCLUDED_)
18
#define AFX_SCWB_H__D38D2415_AB4A_11D6_BB1E_000000000000__INCLUDED_
19
 
20
#if _MSC_VER > 1000
21
#pragma once
22
#endif // _MSC_VER > 1000
23
#include <systemc.h>
24
#include "scRegisterFile.h"
25
class scWB : public sc_module
26
{
27
        public:
28
        sc_in<bool>         in_b_Clock;
29
        sc_in<bool>         in_b_excute;
30
        sc_in<REGS>         in_Rd;
31
        sc_in<uint32_t>     in_n_Result;
32
        sc_in<REGS>         in_Rn;
33
        sc_in<uint32_t>     in_n_Rn;
34
        sc_in<bool>        in_b_W_Rd;//if write Rd?
35
        sc_in<bool>         in_b_WB;
36
        //regs
37
        sc_outmaster    <bool> out_b_RW1;// 0-Read  1-Write
38
        sc_outmaster<REGS>     out_REG1;
39
        sc_inoutslave<uint32_t> inout_n_Data1;
40
        sc_outmaster    <bool> out_b_RW2;// 0-Read  1-Write
41
        sc_outmaster<REGS>     out_REG2;
42
        sc_inoutslave<uint32_t> inout_n_Data2;
43
 
44
 
45
public:
46
        void delay1();
47
        void out_delay();
48
        void regs();
49
 
50
        void entry();
51
        SC_HAS_PROCESS(scWB);
52
        scWB(sc_module_name);
53
        virtual ~scWB();
54
private:
55
        sc_event trigger_wb1,trigger_wb2;
56
        REGS m_Rn;
57
        REGS m_Rd;
58
        uint32_t m_n_Rn;
59
        uint32_t m_n_Rd;
60
        bool m_b_excute;
61
        bool m_b_write;
62
        bool m_b_wb;
63
 
64
};
65
 
66
#endif // !defined(AFX_SCWB_H__D38D2415_AB4A_11D6_BB1E_000000000000__INCLUDED_)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.