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-----------------------------------------------------------------------
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-- This file is part of SCARTS.
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--
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-- SCARTS is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- SCARTS is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with SCARTS. If not, see <http://www.gnu.org/licenses/>.
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-----------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : 7 Segment Display Architecture
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-- Project : SCARTS - Scalable Processor for Embedded Applications in
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-- Realtime Environment
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-------------------------------------------------------------------------------
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-- File : ext_display7seg.vhd
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-- Author : Dipl. Ing. Martin Delvai
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-- Company : TU Wien - Institut fr Technische Informatik
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-- Created : 2002-04-16
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-- Last update: 2009-04-29
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-- Platform : SUN Solaris
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-------------------------------------------------------------------------------
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-- Description:
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-- Dieses Module kann zum Ansteuern eines vierstelligen 7 Segment Modules verwendet
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-- werden. Die vier Anzeigen werden gemultiplext angesteuer.
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-- Durch einen Prescaler kann man die Frequenz des weiterschaltens einsetellen.
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-- Zus?zlich besitzt es noch einen 8 Bit Ausgang zum Ansteuern von z.B. LEDs
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-------------------------------------------------------------------------------
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-- Copyright (c) 2002
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2002-04-16 1.0 delvai Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.pkg_basic.all;
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use work.pkg_scarts.all;
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use work.pkg_counter.all;
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architecture behaviour of ext_counter is
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subtype BYTE is std_logic_vector(7 downto 0);
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type register_set is array (0 to 3) of BYTE;
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constant STATUSREG_CUST : integer := 1;
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constant CONFIGREG_CUST : integer := 3;
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constant ZEROVALUE : std_logic_vector(15 downto 0) := (others => '0');
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constant COUNTER_BYTE0 : integer := 4;
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constant COUNTER_BYTE1 : integer := 5;
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constant COUNTER_BYTE2 : integer := 6;
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constant COUNTER_BYTE3 : integer := 7;
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type reg_type is record
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ifacereg : register_set;
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counter : std_logic_vector(31 downto 0);
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end record;
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signal r_next : reg_type;
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signal r : reg_type :=
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(
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ifacereg => (others => (others => '0')),
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counter => (others => '0')
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);
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signal rstint : std_ulogic;
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begin
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comb : process(r, exti, extsel)
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variable v : reg_type;
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begin
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v := r;
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--schreiben
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if ((extsel = '1') and (exti.write_en = '1')) then
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case exti.addr(4 downto 2) is
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when "000" =>
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if ((exti.byte_en(0) = '1') or (exti.byte_en(1) = '1')) then
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v.ifacereg(STATUSREG)(STA_INT) := '1';
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v.ifacereg(CONFIGREG)(CONF_INTA) :='0';
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else
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if ((exti.byte_en(2) = '1')) then
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v.ifacereg(2) := exti.data(23 downto 16);
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end if;
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if ((exti.byte_en(3) = '1')) then
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v.ifacereg(3) := exti.data(31 downto 24);
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end if;
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end if;
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when "001" =>
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if ((exti.byte_en(0) = '1')) then
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v.counter(7 downto 0) := exti.data(7 downto 0);
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end if;
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if ((exti.byte_en(1) = '1')) then
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v.counter(15 downto 8) := exti.data(15 downto 8);
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end if;
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if ((exti.byte_en(2) = '1')) then
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v.counter(23 downto 16) := exti.data(23 downto 16);
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end if;
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if ((exti.byte_en(3) = '1')) then
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v.counter(31 downto 24) := exti.data(31 downto 24);
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end if;
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when others =>
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null;
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end case;
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end if;
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--auslesen
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exto.data <= (others => '0');
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if ((extsel = '1') and (exti.write_en = '0')) then
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case exti.addr(4 downto 2) is
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when "000" =>
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exto.data <= r.ifacereg(3) & r.ifacereg(2) & r.ifacereg(1) & r.ifacereg(0);
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when "001" =>
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if (r.ifacereg(CONFIGREG)(CONF_ID) = '1') then
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exto.data <= MODULE_VER & MODULE_ID;
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else
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exto.data <= r.counter;
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end if;
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when others =>
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null;
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end case;
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end if;
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--berechnen der neuen status flags
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v.ifacereg(STATUSREG)(STA_LOOR) := r.ifacereg(CONFIGREG)(CONF_LOOW);
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v.ifacereg(STATUSREG)(STA_FSS) := '0';
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v.ifacereg(STATUSREG)(STA_RESH) := '0';
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v.ifacereg(STATUSREG)(STA_RESL) := '0';
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v.ifacereg(STATUSREG)(STA_BUSY) := '0';
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v.ifacereg(STATUSREG)(STA_ERR) := '0';
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v.ifacereg(STATUSREG)(STA_RDY) := '1';
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-- Output soll Defaultmassig auf eingeschalten sie
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v.ifacereg(CONFIGREG)(CONF_OUTD) := '1';
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--soft- und hard-reset vereinen
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rstint <= not RST_ACT;
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if exti.reset = RST_ACT or r.ifacereg(CONFIGREG)(CONF_SRES) = '1' then
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rstint <= RST_ACT;
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end if;
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-- Interrupt
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if r.ifacereg(STATUSREG)(STA_INT) = '1' and r.ifacereg(CONFIGREG)(CONF_INTA) ='0' then
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v.ifacereg(STATUSREG)(STA_INT) := '0';
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end if;
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exto.intreq <= r.ifacereg(STATUSREG)(STA_INT);
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--module specific part
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v.counter := r.counter;
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if r.ifacereg(MY_CONFIGREG)(CMD_COUNT) = '1' then
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v.counter := STD_LOGIC_VECTOR(UNSIGNED(r.counter) + 1);
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elsif r.ifacereg(MY_CONFIGREG)(CMD_CLEAR) = '1' then
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v.counter := (others => '0');
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end if;
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r_next <= v;
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end process;
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reg : process(clk)
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begin
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if rising_edge(clk) then
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if rstint = RST_ACT then
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r.ifacereg <= (others => (others => '0'));
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r.counter <= (others => '0');
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else
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r <= r_next;
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end if;
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end if;
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end process;
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end behaviour;
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