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[/] [scarts/] [trunk/] [processor/] [VHDL/] [ext_modules/] [ext_key_matrix/] [debounce/] [simulation/] [debounce_tb.vhd] - Blame information for rev 3

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1 3 jlechner
-----------------------------------------------------------------------
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-- This file is part of SCARTS.
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-- 
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-- SCARTS is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- 
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-- SCARTS is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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-- GNU General Public License for more details.
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-- 
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-- You should have received a copy of the GNU General Public License
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-- along with SCARTS.  If not, see <http://www.gnu.org/licenses/>.
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity debounce_tb is
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end entity debounce_tb;
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architecture sim of debounce_tb is
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  component debounce_top is
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    port
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    (
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      sys_clk : in std_logic;
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      sys_res_n : in std_logic;
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      btn_a : in std_logic;
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      seg_a : out std_logic_vector(6 downto 0);
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      seg_b : out std_logic_vector(6 downto 0)
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    );
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  end component debounce_top;
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  signal sys_clk, sys_res_n : std_logic;
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  signal btn_a : std_logic;
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  signal seg_a, seg_b : std_logic_vector(6 downto 0);
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  signal stop : boolean := false;
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begin
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  uut : debounce_top
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    port map
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    (
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      sys_clk => sys_clk,
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      sys_res_n => sys_res_n,
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      btn_a => btn_a,
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      seg_a => seg_a,
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      seg_b => seg_b
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    );
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  process
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  begin
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    sys_clk <= '0';
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    wait for 15 ns;
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    sys_clk <= '1';
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    if stop = true then
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      wait;
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    end if;
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    wait for 15 ns;
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  end process;
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  process
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  begin
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    sys_res_n <= '0';
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    btn_a <= '1';
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    wait for 100 ns;
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    sys_res_n <= '1';
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    wait for 2 ms;
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    btn_a <= '0';
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    wait for 100 us;
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    btn_a <= '1';
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    wait for 50 us;
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    btn_a <= '0';
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    wait for 150 us;
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    btn_a <= '1';
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    wait for 25 us;
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    btn_a <= '0';
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    wait for 175 us;
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    btn_a <= '1';
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    wait for 1 us;
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    btn_a <= '0';
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    wait for 2 ms;
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    btn_a <= '1';
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    wait for 100 us;
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    btn_a <= '0';
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    wait for 50 us;
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    btn_a <= '1';
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    wait for 150 us;
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    btn_a <= '0';
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    wait for 25 us;
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    btn_a <= '1';
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    wait for 175 us;
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    btn_a <= '0';
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    wait for 1 us;
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    btn_a <= '1';
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    wait for 2 ms;
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    btn_a <= '0';
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    wait for 100 us;
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    btn_a <= '1';
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    wait for 50 us;
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    btn_a <= '0';
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    wait for 150 us;
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    btn_a <= '1';
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    wait for 25 us;
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    btn_a <= '0';
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    wait for 175 us;
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    btn_a <= '1';
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    wait for 1 us;
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    btn_a <= '0';
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    wait for 2 ms;
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    stop <= true;
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    wait;
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  end process;
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end architecture sim;

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