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[/] [scarts/] [trunk/] [processor/] [VHDL/] [ext_modules/] [ext_key_matrix/] [key_matrix/] [sim/] [key_matrix_tb.vhd] - Blame information for rev 3

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1 3 jlechner 
-----------------------------------------------------------------------
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-- This file is part of SCARTS.
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--
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-- SCARTS is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- SCARTS is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with SCARTS.  If not, see <http://www.gnu.org/licenses/>.
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.key_matrix_pkg.all;
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use work.testbench_util_pkg.all;
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entity key_matrix_tb is
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end entity key_matrix_tb;
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architecture sim of key_matrix_tb is
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  constant CLK_FREQ : integer := 25000000;
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  signal sys_clk, sys_res_n : std_logic;
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  signal columns : std_logic_vector(2 downto 0);
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  signal rows : std_logic_vector(3 downto 0);
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  signal key : std_logic_vector(3 downto 0);
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  signal stop : boolean := false;
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begin
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  uut : key_matrix
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    generic map
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    (
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      CLK_FREQ => CLK_FREQ / 1000,
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      SCAN_TIME_INTERVAL => 100 ms,
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      DEBOUNCE_TIMEOUT => 1 ms,
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      SYNC_STAGES => 2,
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      COLUMN_COUNT => 3,
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      ROW_COUNT => 4
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    )
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    port map
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    (
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      sys_clk => sys_clk,
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      sys_res_n => sys_res_n,
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      columns => columns,
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      rows => rows,
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      key => key
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    );
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  process
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  begin
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    sys_clk <= '0';
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    wait for 1 sec/CLK_FREQ;
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    sys_clk <= '1';
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    if stop = true then
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      wait;
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    end if;
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    wait for 1 sec/CLK_FREQ;
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  end process;
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  process
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  begin
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    sys_res_n <= '0';
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    rows <= (others => '0');
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    wait_cycle(sys_clk, 100);
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    sys_res_n <= '1';
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    wait_cycle(sys_clk, 10010);
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    rows(0) <= '1';
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    wait_cycle(sys_clk, 5);
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    rows(0) <= '0';
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    wait_cycle(sys_clk, 5);
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    rows(0) <= '1';
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    wait_cycle(sys_clk, 5);
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    rows(0) <= '0';
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    wait_cycle(sys_clk, 5);
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    rows(0) <= '1';
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    wait_cycle(sys_clk, 100);
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    rows(0) <= '0';
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    wait_cycle(sys_clk, 5);
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    rows(0) <= '1';
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    wait_cycle(sys_clk, 5);
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    rows(0) <= '0';
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    wait_cycle(sys_clk, 5);
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    rows(0) <= '1';
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    wait_cycle(sys_clk, 5);
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    rows(0) <= '0';
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    wait_cycle(sys_clk, 100);
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    rows(1) <= '1';
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    wait_cycle(sys_clk, 5);
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    rows(1) <= '0';
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    wait_cycle(sys_clk, 5);
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    rows(1) <= '1';
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    wait_cycle(sys_clk, 5);
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    rows(1) <= '0';
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    wait_cycle(sys_clk, 5);
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    rows(1) <= '1';
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    wait_cycle(sys_clk, 100);
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    rows(1) <= '0';
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    wait_cycle(sys_clk, 5);
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    rows(1) <= '1';
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    wait_cycle(sys_clk, 5);
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    rows(1) <= '0';
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    wait_cycle(sys_clk, 5);
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    rows(1) <= '1';
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    wait_cycle(sys_clk, 5);
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    rows(1) <= '0';
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    wait_cycle(sys_clk, 100);
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    rows(2) <= '1';
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    wait_cycle(sys_clk, 5);
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    rows(2) <= '0';
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    wait_cycle(sys_clk, 5);
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    rows(2) <= '1';
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    wait_cycle(sys_clk, 5);
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    rows(2) <= '0';
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    wait_cycle(sys_clk, 5);
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    rows(2) <= '1';
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    wait_cycle(sys_clk, 100);
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    rows(2) <= '0';
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    wait_cycle(sys_clk, 5);
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    rows(2) <= '1';
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    wait_cycle(sys_clk, 5);
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    rows(2) <= '0';
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    wait_cycle(sys_clk, 5);
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    rows(2) <= '1';
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    wait_cycle(sys_clk, 5);
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    rows(2) <= '0';
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    wait_cycle(sys_clk, 100);
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    rows(3) <= '1';
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    wait_cycle(sys_clk, 5);
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    rows(3) <= '0';
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    wait_cycle(sys_clk, 5);
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    rows(3) <= '1';
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    wait_cycle(sys_clk, 5);
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    rows(3) <= '0';
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    wait_cycle(sys_clk, 5);
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    rows(3) <= '1';
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    wait_cycle(sys_clk, 100);
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    rows(3) <= '0';
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    wait_cycle(sys_clk, 5);
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    rows(3) <= '1';
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    wait_cycle(sys_clk, 5);
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    rows(3) <= '0';
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    wait_cycle(sys_clk, 5);
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    rows(3) <= '1';
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    wait_cycle(sys_clk, 5);
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    rows(3) <= '0';
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    wait_cycle(sys_clk, 1550);
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    rows(0) <= '1';
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    wait_cycle(sys_clk, 5);
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    rows(0) <= '0';
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    wait_cycle(sys_clk, 5);
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    rows(0) <= '1';
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    wait_cycle(sys_clk, 5);
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    rows(0) <= '0';
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    wait_cycle(sys_clk, 5);
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    rows(0) <= '1';
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    wait_cycle(sys_clk, 75);
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    rows(0) <= '0';
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    wait_cycle(sys_clk, 10000);
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    stop <= true;
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    wait;
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  end process;
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end architecture sim;

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