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-----------------------------------------------------------------------
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-- This file is part of SCARTS.
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--
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-- SCARTS is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- SCARTS is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with SCARTS. If not, see <http://www.gnu.org/licenses/>.
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-----------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : miniUART Baud Rate Generator
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-- Module : ext_miniUART
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-- Project : HW/SW-Codesign
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-------------------------------------------------------------------------------
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-- File : miniUART_brg.vhd
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-- Author : Roman Seiger
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-- Company : TU Wien - Institut für Technische Informatik
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-- Created : 2005-03-08
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-- Last update: 2007-05-28
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-------------------------------------------------------------------------------
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-- TODO: OVERFLOWWIDTH ist nicht konsistent!!!
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----------------------------------------------------------------------------------
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-- LIBRARY
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----------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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USE IEEE.std_logic_arith.all;
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use IEEE.std_logic_UNSIGNED.all;
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use work.pkg_basic.all;
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use work.pkg_miniUART.all;
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----------------------------------------------------------------------------------
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-- ENTITY
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----------------------------------------------------------------------------------
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entity miniUART_BRG is
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port (
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clk : in std_logic;
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reset : in std_logic;
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StartTrans : in std_logic; -- Transmitterpulse eingeschaltet?
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StartRec : in std_logic; -- Receiverpulse eingeschaltet?
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UBRS : in std_logic_vector(15 downto 0); -- Baud Rate Selection Register
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-- (12 bit ganzzahlig, 4 bit fraction)
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tp : out std_logic; -- Transmitterpulse
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rp : out std_logic -- Receiverpulse
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);
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end miniUART_BRG;
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----------------------------------------------------------------------------------
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-- ARCHITECTURE
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----------------------------------------------------------------------------------
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architecture behaviour of miniUART_BRG is
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-- Zählerbreite (11bit aus UBRS + 1bit Überlaufschutz)
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constant COUNTERWIDTH : integer := 12;
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-- Zählerkonstanten
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constant COUNTER_ZERO : std_logic_vector(COUNTERWIDTH-1 downto 0) := (0 => '1', others => '0');
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-- Überlaufregisterbreite (4bit aus UBRS + 1bit Überlauf)
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constant OVERFLOWWIDTH : integer := 6;
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-- interne Signale zur Zwischenspeicherung der Eingänge
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signal UBRS_i, UBRS_nxt : std_logic_vector(16 downto 0);
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-- Zähler
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signal counter : std_logic_vector(COUNTERWIDTH-1 downto 0);
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signal next_counter : std_logic_vector(COUNTERWIDTH-1 downto 0);
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-- Überlaufregister
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signal overflow : std_logic_vector(OVERFLOWWIDTH-1 downto 0);
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signal next_overflow : std_logic_vector(OVERFLOWWIDTH-1 downto 0);
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-- Transmitpulse oder Receivepulse?
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signal pulse_toggle : std_logic;
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signal next_pulse_toggle : std_logic;
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begin -- behaviour
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BRG_COUNTER: process (clk, reset)
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begin -- process BRG_COUNTER
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-- ausgeschaltet, entspricht reset
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if reset = RST_ACT then
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counter <= COUNTER_ZERO;
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overflow(4 downto 0) <= (others => '0');-- UBRS(4 downto 0);
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overflow(OVERFLOWWIDTH-1) <= '0';
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UBRS_i(16) <= '0';
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UBRS_i(15 downto 0) <= (others => '1'); --UBRS; -- UBRS übernehmen
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pulse_toggle <= '0'; -- Transmitter zuerst!
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-- in Betrieb, runterzählen
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elsif (clk'event and clk = '1') then
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counter <= next_counter;
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overflow <= next_overflow;
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UBRS_i <= UBRS_nxt;
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pulse_toggle <= next_pulse_toggle;
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end if;
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end process BRG_COUNTER;
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BRG_CALC_NEXT: process (counter, overflow, UBRS_i, UBRS, StartTrans,
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StartRec, pulse_toggle)
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begin -- process BRG_CALC_NEXT
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-- Defaultwerte
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tp <= '0';
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rp <= '0';
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UBRS_nxt <= UBRS_i;
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-- counter weiterzählen
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next_counter <= counter - '1';
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next_overflow <= overflow;
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-- pulse_toggle halten
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next_pulse_toggle <= pulse_toggle;
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if (StartTrans /= BRG_ON) and (StartRec /= BRG_ON) then
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next_counter <= COUNTER_ZERO;
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next_overflow(4 downto 0) <= UBRS(4 downto 0);
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next_overflow(OVERFLOWWIDTH-1) <= '0';
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next_pulse_toggle <= '0';
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UBRS_nxt(16) <= '0';
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UBRS_nxt(15 downto 0) <= UBRS;
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-- counter zurücksetzen, neues overflow berechnen
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elsif counter = COUNTER_ZERO then
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next_counter <= UBRS_i(16 downto 5) + overflow(5);
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next_overflow <= (overflow and "011111") + UBRS_i(4 downto 0);
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-- Pulses ausgeben
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tp <= (not pulse_toggle) and StartTrans;
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rp <= pulse_toggle and StartRec;
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next_pulse_toggle <= not pulse_toggle;
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end if;
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end process BRG_CALC_NEXT;
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end behaviour;
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