1 |
3 |
jlechner |
-----------------------------------------------------------------------
|
2 |
|
|
-- This file is part of SCARTS.
|
3 |
|
|
--
|
4 |
|
|
-- SCARTS is free software: you can redistribute it and/or modify
|
5 |
|
|
-- it under the terms of the GNU General Public License as published by
|
6 |
|
|
-- the Free Software Foundation, either version 3 of the License, or
|
7 |
|
|
-- (at your option) any later version.
|
8 |
|
|
--
|
9 |
|
|
-- SCARTS is distributed in the hope that it will be useful,
|
10 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
11 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
12 |
|
|
-- GNU General Public License for more details.
|
13 |
|
|
--
|
14 |
|
|
-- You should have received a copy of the GNU General Public License
|
15 |
|
|
-- along with SCARTS. If not, see <http://www.gnu.org/licenses/>.
|
16 |
|
|
-----------------------------------------------------------------------
|
17 |
|
|
|
18 |
|
|
|
19 |
|
|
-------------------------------------------------------------------------------
|
20 |
|
|
-- Title : Template for Extension Module
|
21 |
|
|
-- Project : SCARTS - Scalable Processor for Embedded Applications in
|
22 |
|
|
-- Realtime Environment
|
23 |
|
|
-------------------------------------------------------------------------------
|
24 |
|
|
-- File : ext_generic.vhd
|
25 |
|
|
-- Author : Martin Delvai
|
26 |
|
|
-- Company : TU Wien - Institut fr Technische Informatik
|
27 |
|
|
-- Created : 2007/04/16
|
28 |
|
|
-- Last update: 2007-08-21
|
29 |
|
|
-- Platform : Linux
|
30 |
|
|
-------------------------------------------------------------------------------
|
31 |
|
|
-- Description:
|
32 |
|
|
-------------------------------------------------------------------------------
|
33 |
|
|
-- Copyright (c) 2007
|
34 |
|
|
-------------------------------------------------------------------------------
|
35 |
|
|
-- Revisions :
|
36 |
|
|
-- Date Version Author Description
|
37 |
|
|
-- 2007-04-16 1.0 delvai Created
|
38 |
|
|
-------------------------------------------------------------------------------
|
39 |
|
|
|
40 |
|
|
library ieee;
|
41 |
|
|
use ieee.std_logic_1164.all;
|
42 |
|
|
use ieee.numeric_std.all;
|
43 |
|
|
|
44 |
|
|
use work.pkg_basic.all;
|
45 |
|
|
use work.pkg_timer.all;
|
46 |
|
|
|
47 |
|
|
|
48 |
|
|
architecture behaviour of ext_timer is
|
49 |
|
|
|
50 |
|
|
subtype BYTE is std_logic_vector(7 downto 0);
|
51 |
|
|
type register_set is array (0 to 19) of BYTE;
|
52 |
|
|
|
53 |
|
|
signal clk_cnt_nxt, inst_cnt_nxt : std_logic_vector(31 downto 0);
|
54 |
|
|
signal clk_match_nxt, inst_match_nxt : std_logic_vector(31 downto 0);
|
55 |
|
|
signal start_i_nxt, start_c_nxt : std_logic;
|
56 |
|
|
signal stop_i_nxt, stop_c_nxt : std_logic;
|
57 |
|
|
signal cint_nxt, iint_nxt : std_logic;
|
58 |
|
|
|
59 |
|
|
|
60 |
|
|
type reg_type is record
|
61 |
|
|
ifacereg : register_set;
|
62 |
|
|
end record;
|
63 |
|
|
|
64 |
|
|
|
65 |
|
|
signal r, r_next : reg_type;
|
66 |
|
|
signal rstint : std_ulogic;
|
67 |
|
|
|
68 |
|
|
begin
|
69 |
|
|
|
70 |
|
|
-- Synchronous process
|
71 |
|
|
reg : process(clk, rstint)
|
72 |
|
|
begin
|
73 |
|
|
if rstint = RST_ACT then
|
74 |
|
|
for i in 0 to 19 loop
|
75 |
|
|
r.ifacereg(i) <= (others => '0');
|
76 |
|
|
end loop;
|
77 |
|
|
elsif rising_edge(clk) then
|
78 |
|
|
|
79 |
|
|
r <= r_next;
|
80 |
|
|
|
81 |
|
|
end if;
|
82 |
|
|
end process;
|
83 |
|
|
|
84 |
|
|
|
85 |
|
|
comb : process(r, exti, extsel, clk_cnt_nxt, clk_match_nxt, inst_match_nxt,
|
86 |
|
|
inst_cnt_nxt, stop_c_nxt, stop_i_nxt, start_c_nxt, start_i_nxt,
|
87 |
|
|
cint_nxt, iint_nxt)
|
88 |
|
|
|
89 |
|
|
variable v : reg_type;
|
90 |
|
|
variable clk_cnt_v, inst_cnt_v : std_logic_vector(31 downto 0);
|
91 |
|
|
variable clk_match_v, inst_match_v : std_logic_vector(31 downto 0);
|
92 |
|
|
|
93 |
|
|
begin
|
94 |
|
|
-- Default Values
|
95 |
|
|
v := r;
|
96 |
|
|
|
97 |
|
|
|
98 |
|
|
--berechnen der neuen status flags
|
99 |
|
|
v.ifacereg(STATUSREG)(STA_LOOR) := r.ifacereg(CONFIGREG)(CONF_LOOW);
|
100 |
|
|
v.ifacereg(STATUSREG)(STA_FSS) := '0';
|
101 |
|
|
v.ifacereg(STATUSREG)(STA_RESH) := '0';
|
102 |
|
|
v.ifacereg(STATUSREG)(STA_RESL) := '0';
|
103 |
|
|
v.ifacereg(STATUSREG)(STA_BUSY) := '0';
|
104 |
|
|
v.ifacereg(STATUSREG)(STA_ERR) := '0';
|
105 |
|
|
v.ifacereg(STATUSREG)(STA_RDY) := '1';
|
106 |
|
|
|
107 |
|
|
--Merging soft- and hard-reset
|
108 |
|
|
rstint <= not RST_ACT;
|
109 |
|
|
if exti.reset = RST_ACT or r.ifacereg(CONFIGREG)(CONF_SRES) = '1' then
|
110 |
|
|
rstint <= RST_ACT;
|
111 |
|
|
end if;
|
112 |
|
|
|
113 |
|
|
--Interrupt Behandlung
|
114 |
|
|
|
115 |
|
|
if r.ifacereg(CONFIGREG)(CONF_INTA) = '1' then
|
116 |
|
|
v.ifacereg(STATUSREG)(STA_INT) := '0';
|
117 |
|
|
v.ifacereg(CONFIGREG)(CONF_INTA) := '0';
|
118 |
|
|
end if;
|
119 |
|
|
|
120 |
|
|
exto.intreq <= r.ifacereg(STATUSREG)(STA_INT);
|
121 |
|
|
|
122 |
|
|
|
123 |
|
|
--end process;
|
124 |
|
|
|
125 |
|
|
|
126 |
|
|
-- Module Specific part
|
127 |
|
|
|
128 |
|
|
-- mod_specific: process (r)
|
129 |
|
|
-- begin -- process mod_specific
|
130 |
|
|
|
131 |
|
|
clk_cnt_v(7 downto 0) := r.ifacereg(CLK_CNT_0);
|
132 |
|
|
clk_cnt_v(15 downto 8) := r.ifacereg(CLK_CNT_1);
|
133 |
|
|
clk_cnt_v(23 downto 16) := r.ifacereg(CLK_CNT_2);
|
134 |
|
|
clk_cnt_v(31 downto 24) := r.ifacereg(CLK_CNT_3);
|
135 |
|
|
|
136 |
|
|
clk_match_v(7 downto 0) := r.ifacereg(CLK_MATCH_0);
|
137 |
|
|
clk_match_v(15 downto 8) := r.ifacereg(CLK_MATCH_1);
|
138 |
|
|
clk_match_v(23 downto 16) := r.ifacereg(CLK_MATCH_2);
|
139 |
|
|
clk_match_v(31 downto 24) := r.ifacereg(CLK_MATCH_3);
|
140 |
|
|
|
141 |
|
|
inst_cnt_v(7 downto 0) := r.ifacereg(INST_CNT_0);
|
142 |
|
|
inst_cnt_v(15 downto 8) := r.ifacereg(INST_CNT_1);
|
143 |
|
|
inst_cnt_v(23 downto 16) := r.ifacereg(INST_CNT_2);
|
144 |
|
|
inst_cnt_v(31 downto 24) := r.ifacereg(INST_CNT_3);
|
145 |
|
|
|
146 |
|
|
inst_match_v(7 downto 0) := r.ifacereg(INST_MATCH_0);
|
147 |
|
|
inst_match_v(15 downto 8) := r.ifacereg(INST_MATCH_1);
|
148 |
|
|
inst_match_v(23 downto 16) := r.ifacereg(INST_MATCH_2);
|
149 |
|
|
inst_match_v(31 downto 24) := r.ifacereg(INST_MATCH_3);
|
150 |
|
|
|
151 |
|
|
cint_nxt <= '0';
|
152 |
|
|
iint_nxt <= '0';
|
153 |
|
|
|
154 |
|
|
start_i_nxt <= r.ifacereg(CONFIG_C)(START_I);
|
155 |
|
|
start_c_nxt <= r.ifacereg(CONFIG_C)(START_C);
|
156 |
|
|
|
157 |
|
|
stop_i_nxt <= r.ifacereg(CONFIG_C)(STOP_I);
|
158 |
|
|
stop_c_nxt <= r.ifacereg(CONFIG_C)(STOP_C);
|
159 |
|
|
|
160 |
|
|
|
161 |
|
|
clk_cnt_nxt <= (others => '0');
|
162 |
|
|
inst_cnt_nxt <= (others => '0');
|
163 |
|
|
|
164 |
|
|
clk_match_nxt <= clk_match_v;
|
165 |
|
|
inst_match_nxt <= inst_match_v;
|
166 |
|
|
|
167 |
|
|
|
168 |
|
|
if r.ifacereg(CONFIG_C)(START_C)='1' then
|
169 |
|
|
clk_cnt_nxt <= std_logic_vector(unsigned(clk_cnt_v) + 1);
|
170 |
|
|
end if;
|
171 |
|
|
|
172 |
|
|
if r.ifacereg(CONFIG_C)(START_I)='1' then
|
173 |
|
|
inst_cnt_nxt <= std_logic_vector(unsigned(inst_cnt_v) + 1);
|
174 |
|
|
end if;
|
175 |
|
|
|
176 |
|
|
if r.ifacereg(CONFIG_C)(STOP_C)='1' then
|
177 |
|
|
clk_cnt_nxt <= clk_cnt_v;
|
178 |
|
|
end if;
|
179 |
|
|
|
180 |
|
|
if r.ifacereg(CONFIG_C)(STOP_I)='1' then
|
181 |
|
|
inst_cnt_nxt <= inst_cnt_v;
|
182 |
|
|
end if;
|
183 |
|
|
|
184 |
|
|
if clk_cnt_v = clk_match_v and r.ifacereg(STATUS_C)(CINT) = '0' then
|
185 |
|
|
if r.ifacereg(CONFIG_C)(CMI) = '1' then
|
186 |
|
|
cint_nxt <= '1';
|
187 |
|
|
end if;
|
188 |
|
|
|
189 |
|
|
if r.ifacereg(CONFIG_C)(MCI)= '1' then
|
190 |
|
|
inst_match_nxt <= inst_cnt_v;
|
191 |
|
|
end if;
|
192 |
|
|
|
193 |
|
|
start_c_nxt <= '0';
|
194 |
|
|
stop_c_nxt <= '0';
|
195 |
|
|
|
196 |
|
|
end if;
|
197 |
|
|
|
198 |
|
|
if inst_cnt_v = inst_match_v and r.ifacereg(STATUS_C)(IINT) = '0' then
|
199 |
|
|
if r.ifacereg(CONFIG_C)(IMI) = '1' then
|
200 |
|
|
iint_nxt <= '1';
|
201 |
|
|
end if;
|
202 |
|
|
|
203 |
|
|
if r.ifacereg(CONFIG_C)(MCC)= '1' then
|
204 |
|
|
clk_match_nxt <= clk_cnt_v;
|
205 |
|
|
end if;
|
206 |
|
|
|
207 |
|
|
start_i_nxt <= '0';
|
208 |
|
|
stop_i_nxt <= '0';
|
209 |
|
|
|
210 |
|
|
end if;
|
211 |
|
|
-- Module specific output
|
212 |
|
|
|
213 |
|
|
v.ifacereg(CLK_CNT_0) := clk_cnt_nxt(7 downto 0) ;
|
214 |
|
|
v.ifacereg(CLK_CNT_1) := clk_cnt_nxt(15 downto 8) ;
|
215 |
|
|
v.ifacereg(CLK_CNT_2) := clk_cnt_nxt(23 downto 16) ;
|
216 |
|
|
v.ifacereg(CLK_CNT_3) := clk_cnt_nxt(31 downto 24) ;
|
217 |
|
|
|
218 |
|
|
v.ifacereg(CLK_MATCH_0) := clk_match_nxt(7 downto 0) ;
|
219 |
|
|
v.ifacereg(CLK_MATCH_1) := clk_match_nxt(15 downto 8) ;
|
220 |
|
|
v.ifacereg(CLK_MATCH_2) := clk_match_nxt(23 downto 16) ;
|
221 |
|
|
v.ifacereg(CLK_MATCH_3) := clk_match_nxt(31 downto 24) ;
|
222 |
|
|
|
223 |
|
|
v.ifacereg(INST_CNT_0) := inst_cnt_nxt(7 downto 0) ;
|
224 |
|
|
v.ifacereg(INST_CNT_1) := inst_cnt_nxt(15 downto 8) ;
|
225 |
|
|
v.ifacereg(INST_CNT_2) := inst_cnt_nxt(23 downto 16) ;
|
226 |
|
|
v.ifacereg(INST_CNT_3) := inst_cnt_nxt(31 downto 24) ;
|
227 |
|
|
|
228 |
|
|
v.ifacereg(INST_MATCH_0) := inst_match_nxt(7 downto 0) ;
|
229 |
|
|
v.ifacereg(INST_MATCH_1) := inst_match_nxt(15 downto 8) ;
|
230 |
|
|
v.ifacereg(INST_MATCH_2) := inst_match_nxt(23 downto 16) ;
|
231 |
|
|
v.ifacereg(INST_MATCH_3) := inst_match_nxt(31 downto 24) ;
|
232 |
|
|
|
233 |
|
|
v.ifacereg(CONFIG_C)(START_I) := start_i_nxt ;
|
234 |
|
|
v.ifacereg(CONFIG_C)(START_C) := start_c_nxt ;
|
235 |
|
|
|
236 |
|
|
v.ifacereg(CONFIG_C)(STOP_I) := stop_i_nxt ;
|
237 |
|
|
v.ifacereg(CONFIG_C)(STOP_C) := stop_c_nxt ;
|
238 |
|
|
|
239 |
|
|
v.ifacereg(STATUS_C)(IINT) := iint_nxt;
|
240 |
|
|
v.ifacereg(STATUS_C)(CINT) := cint_nxt;
|
241 |
|
|
|
242 |
|
|
v.ifacereg(STATUSREG)(STA_INT) := cint_nxt or iint_nxt;
|
243 |
|
|
|
244 |
|
|
-- Begin: Neues Interface
|
245 |
|
|
-- schreiben
|
246 |
|
|
if ((extsel = '1') and (exti.write_en = '1')) then
|
247 |
|
|
case exti.addr(4 downto 2) is
|
248 |
|
|
when "000" =>
|
249 |
|
|
if ((exti.byte_en(0) = '1') or (exti.byte_en(1) = '1')) then
|
250 |
|
|
v.ifacereg(STATUSREG)(STA_INT) := '1';
|
251 |
|
|
v.ifacereg(CONFIGREG)(CONF_INTA) :='0';
|
252 |
|
|
else
|
253 |
|
|
if ((exti.byte_en(2) = '1')) then
|
254 |
|
|
v.ifacereg(2) := exti.data(23 downto 16);
|
255 |
|
|
end if;
|
256 |
|
|
if ((exti.byte_en(3) = '1')) then
|
257 |
|
|
v.ifacereg(3) := exti.data(31 downto 24);
|
258 |
|
|
end if;
|
259 |
|
|
end if;
|
260 |
|
|
|
261 |
|
|
when "001" =>
|
262 |
|
|
if ((exti.byte_en(0) = '1')) then
|
263 |
|
|
v.ifacereg(4) := exti.data(7 downto 0);
|
264 |
|
|
end if;
|
265 |
|
|
if ((exti.byte_en(1) = '1')) then
|
266 |
|
|
v.ifacereg(5) := exti.data(15 downto 8);
|
267 |
|
|
end if;
|
268 |
|
|
if ((exti.byte_en(2) = '1')) then
|
269 |
|
|
v.ifacereg(6) := exti.data(23 downto 16);
|
270 |
|
|
end if;
|
271 |
|
|
if ((exti.byte_en(3) = '1')) then
|
272 |
|
|
v.ifacereg(7) := exti.data(31 downto 24);
|
273 |
|
|
end if;
|
274 |
|
|
|
275 |
|
|
when "010" =>
|
276 |
|
|
if ((exti.byte_en(0) = '1')) then
|
277 |
|
|
v.ifacereg(8) := exti.data(7 downto 0);
|
278 |
|
|
end if;
|
279 |
|
|
if ((exti.byte_en(1) = '1')) then
|
280 |
|
|
v.ifacereg(9) := exti.data(15 downto 8);
|
281 |
|
|
end if;
|
282 |
|
|
if ((exti.byte_en(2) = '1')) then
|
283 |
|
|
v.ifacereg(10) := exti.data(23 downto 16);
|
284 |
|
|
end if;
|
285 |
|
|
if ((exti.byte_en(3) = '1')) then
|
286 |
|
|
v.ifacereg(11) := exti.data(31 downto 24);
|
287 |
|
|
end if;
|
288 |
|
|
|
289 |
|
|
when "011" =>
|
290 |
|
|
if ((exti.byte_en(0) = '1')) then
|
291 |
|
|
v.ifacereg(12) := exti.data(7 downto 0);
|
292 |
|
|
end if;
|
293 |
|
|
if ((exti.byte_en(1) = '1')) then
|
294 |
|
|
v.ifacereg(13) := exti.data(15 downto 8);
|
295 |
|
|
end if;
|
296 |
|
|
if ((exti.byte_en(2) = '1')) then
|
297 |
|
|
v.ifacereg(14) := exti.data(23 downto 16);
|
298 |
|
|
end if;
|
299 |
|
|
if ((exti.byte_en(3) = '1')) then
|
300 |
|
|
v.ifacereg(15) := exti.data(31 downto 24);
|
301 |
|
|
end if;
|
302 |
|
|
|
303 |
|
|
when "100" =>
|
304 |
|
|
if ((exti.byte_en(0) = '1')) then
|
305 |
|
|
v.ifacereg(16) := exti.data(7 downto 0);
|
306 |
|
|
end if;
|
307 |
|
|
if ((exti.byte_en(1) = '1')) then
|
308 |
|
|
v.ifacereg(17) := exti.data(15 downto 8);
|
309 |
|
|
end if;
|
310 |
|
|
if ((exti.byte_en(2) = '1')) then
|
311 |
|
|
v.ifacereg(18) := exti.data(23 downto 16);
|
312 |
|
|
end if;
|
313 |
|
|
if ((exti.byte_en(3) = '1')) then
|
314 |
|
|
v.ifacereg(19) := exti.data(31 downto 24);
|
315 |
|
|
end if;
|
316 |
|
|
|
317 |
|
|
when others =>
|
318 |
|
|
null;
|
319 |
|
|
end case;
|
320 |
|
|
end if;
|
321 |
|
|
|
322 |
|
|
--auslesen
|
323 |
|
|
exto.data <= (others => '0');
|
324 |
|
|
if ((extsel = '1') and (exti.write_en = '0')) then
|
325 |
|
|
case exti.addr(4 downto 2) is
|
326 |
|
|
when "000" =>
|
327 |
|
|
exto.data <= r.ifacereg(3) & r.ifacereg(2) & r.ifacereg(1) & r.ifacereg(0);
|
328 |
|
|
when "001" =>
|
329 |
|
|
if (r.ifacereg(CONFIGREG)(CONF_ID) = '1') then
|
330 |
|
|
exto.data <= MODULE_VER & MODULE_ID;
|
331 |
|
|
else
|
332 |
|
|
exto.data <= r.ifacereg(7) & r.ifacereg(6) & r.ifacereg(5) & r.ifacereg(4);
|
333 |
|
|
end if;
|
334 |
|
|
when "010" =>
|
335 |
|
|
exto.data <= r.ifacereg(11) & r.ifacereg(10) & r.ifacereg(9) & r.ifacereg(8);
|
336 |
|
|
when "011" =>
|
337 |
|
|
exto.data <= r.ifacereg(15) & r.ifacereg(14) & r.ifacereg(13) & r.ifacereg(12);
|
338 |
|
|
when "100" =>
|
339 |
|
|
exto.data <= r.ifacereg(19) & r.ifacereg(18) & r.ifacereg(17) & r.ifacereg(16);
|
340 |
|
|
when others =>
|
341 |
|
|
null;
|
342 |
|
|
end case;
|
343 |
|
|
end if;
|
344 |
|
|
-- Ende Neues Interface
|
345 |
|
|
|
346 |
|
|
|
347 |
|
|
|
348 |
|
|
|
349 |
|
|
r_next <= v;
|
350 |
|
|
|
351 |
|
|
end process;
|
352 |
|
|
|
353 |
|
|
end behaviour;
|