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[/] [scarts/] [trunk/] [processor/] [VHDL/] [scarts_core/] [bpt.vhd] - Blame information for rev 3

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1 3 jlechner
-----------------------------------------------------------------------
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-- This file is part of SCARTS.
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-- 
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-- SCARTS is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- 
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-- SCARTS is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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-- GNU General Public License for more details.
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-- 
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-- You should have received a copy of the GNU General Public License
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-- along with SCARTS.  If not, see <http://www.gnu.org/licenses/>.
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-----------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title      : Template for Extension Module
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-- Project    : SCARTS - Scalable Processor for Embedded Applications in
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--              Realtime Environment
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-------------------------------------------------------------------------------
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-- File       : ext_breakpoint.vhd
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-- Author     : Martin Delvai
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-- Company    : TU Wien - Institut fr Technische Informatik
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-- Created    : 2007/04/16
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-- Last update: 2011-03-20
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-- Platform   : Linux
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2007 
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Date        Version  Author  Description
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-- 2007-04-16  1.0      delvai  Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.scarts_core_pkg.all;
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use work.scarts_pkg.all;
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entity ext_breakpoint is
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  generic (
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    CONF : scarts_conf_type);
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  port (
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    -- SCARTS Interface
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    clk                     : IN  std_logic;
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    extsel                  : in std_ulogic;
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    exti                    : in  module_in_type;
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    exto                    : out module_out_type;
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    -- Modul specific interface (= Pins)
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    debugo_wdata     : in  INSTR;
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    debugo_waddr     : in  std_logic_vector(CONF.instr_ram_size-1 downto 0);
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    debugo_wen       : in  std_ulogic;
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    debugo_raddr     : in  std_logic_vector(CONF.instr_ram_size-1 downto 0);
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    debugo_rdata     : in  INSTR;
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    debugo_read_en   : in  std_ulogic;
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    debugo_hi_addr   : in  std_logic_vector(CONF.word_size-1 downto 15);
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    debugi_rdata     : out INSTR;
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    watchpoint_act   : in std_ulogic
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    );
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end ext_breakpoint;
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architecture behaviour of ext_breakpoint is
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subtype BYTE is std_logic_vector(7 downto 0);
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type register_set is array (0 to 31) of BYTE;
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--signal mul_result : std_logic_vector(63 downto 0);
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constant CONFIGREG_CUST : integer := 3;
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type reg_type is record
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  ifacereg  : register_set;
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end record;
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signal r, r_next : reg_type;
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signal do_trap, do_trap_next : std_ulogic;
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signal rstint : std_ulogic;
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begin
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comb : process(r, exti, extsel, debugo_raddr)
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  variable v : reg_type;
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  variable anz: integer range 7 downto 0;
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  variable index: integer range 7 downto 0;
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  variable dummy_addr:std_logic_vector(31 downto 0);
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begin
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  -- Default Values
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  do_trap_next <= '0';
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  v := r;
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  index := to_integer(unsigned(exti.addr(4 downto 2)));
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    --schreiben
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    if ((extsel = '1') and (exti.write_en = '1')) then
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      case exti.addr(4 downto 2) is
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        when "000" =>
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          if ((exti.byte_en(0) = '1') or (exti.byte_en(1) = '1')) then
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            v.ifacereg(STATUSREG)(STA_INT) := '1';
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            v.ifacereg(CONFIGREG)(CONF_INTA) :='0';
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          else
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            if ((exti.byte_en(2) = '1')) then
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              v.ifacereg(2) := exti.data(23 downto 16);
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            end if;
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            if ((exti.byte_en(3) = '1')) then
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              v.ifacereg(3) := exti.data(31 downto 24);
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            end if;
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          end if;
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        when others =>
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          if ((exti.byte_en(0) = '1')) then
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            v.ifacereg(index*4) := exti.data(7 downto 0);
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          end if;
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          if ((exti.byte_en(1) = '1')) then
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            v.ifacereg(index*4+1) := exti.data(15 downto 8);
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          end if;
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          if ((exti.byte_en(2) = '1')) then
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            v.ifacereg(index*4+2) := exti.data(23 downto 16);
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          end if;
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          if ((exti.byte_en(3) = '1')) then
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            v.ifacereg(index*4+3) := exti.data(31 downto 24);
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          end if;
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        --when others =>
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          --null;
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      end case;
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    end if;
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    --auslesen
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    exto.data <= (others => '0');
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    if ((extsel = '1') and (exti.write_en = '0')) then
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      case exti.addr(4 downto 2) is
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        when "000" =>
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          exto.data <= r.ifacereg(3) & r.ifacereg(2) & r.ifacereg(1) & r.ifacereg(0);
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        when "001" =>
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          if (r.ifacereg(CONFIGREG)(CONF_ID) = '1') then
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            exto.data <= MODULE_VER & MODULE_ID;
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          else
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            exto.data <= r.ifacereg(index*4+3) & r.ifacereg(index*4+2)
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                & r.ifacereg(index*4+1) & r.ifacereg(index*4);
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          end if;
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        when others =>
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            exto.data <= r.ifacereg(index*4+3) & r.ifacereg(index*4+2)
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                & r.ifacereg(index*4+1) & r.ifacereg(index*4);
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      end case;
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    end if;
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    --berechnen der neuen status flags
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    v.ifacereg(STATUSREG)(STA_LOOR) := r.ifacereg(CONFIGREG)(CONF_LOOW);
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    v.ifacereg(STATUSREG)(STA_FSS) := '0';
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    v.ifacereg(STATUSREG)(STA_RESH) := '0';
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    v.ifacereg(STATUSREG)(STA_RESL) := '0';
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    v.ifacereg(STATUSREG)(STA_BUSY) := '0';
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    v.ifacereg(STATUSREG)(STA_ERR) := '0';
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    v.ifacereg(STATUSREG)(STA_RDY) := '1';
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    -- Output soll Defaultmassig auf eingeschalten sie 
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    v.ifacereg(CONFIGREG)(CONF_OUTD) := '1';
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    --soft- und hard-reset vereinen
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    rstint <= not RST_ACT;
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    if exti.reset = RST_ACT or r.ifacereg(CONFIGREG)(CONF_SRES) = '1' then
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      rstint <= RST_ACT;
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    end if;
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    --Interrupt Behandlung 
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    if r.ifacereg(CONFIGREG)(CONF_INTA) = '1' then
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      v.ifacereg(STATUSREG)(STA_INT)   := '0';
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      v.ifacereg(CONFIGREG)(CONF_INTA) := '0';
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    end if;
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    exto.intreq <= r.ifacereg(STATUSREG)(STA_INT);
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  -- Module Specific part
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  if r.ifacereg(CONFIGREG_CUST)(6 downto 3) /= "0000" then
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    --Single Stepping. 
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--    if pc /= s_debugo_pc then
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      -- Decrement single-step counter whenever an instruction is executed.
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      v.ifacereg(CONFIGREG_CUST)(6 downto 3) := std_logic_vector(UNSIGNED(r.ifacereg(CONFIGREG_CUST)(6 downto 3)) - 1);
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      if v.ifacereg(CONFIGREG_CUST)(6 downto 3) = "0000" then
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            --Counter reached zero. Raise interrupt.
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            v.ifacereg(STATUSREG)(STA_INT) := '1';
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      end if;
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--    end if;
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  elsif r.ifacereg(CONFIGREG_CUST)(7) = '1' -- Enabled
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    and r.ifacereg(CONFIGREG_CUST)(2 downto 0) /= "000" then
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--    --Compare breakpoint-addresses with current PC.
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    anz := to_integer(UNSIGNED(r.ifacereg(CONFIGREG_CUST)(2 downto 0)));
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    dummy_addr := (others => '0');
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    dummy_addr(CONF.instr_ram_size-1 downto 0) := debugo_raddr;
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    for i in 7 downto 1 loop
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      if anz >= i then
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        if v.ifacereg(4*i + 0) = dummy_addr(7 downto 0)
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          and v.ifacereg(4*i + 1) = dummy_addr(15 downto 8)
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          --Add the next 2 lines for 32-Bit configurations.
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          and (CONF.word_size = 16 or v.ifacereg(4*i + 2) = dummy_addr(23 downto 16))
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          and (CONF.word_size = 16 or v.ifacereg(4*i + 3) = dummy_addr(31 downto 24))
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        then
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          --Breapoint hit. Return TRAP0 as opcode.
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          do_trap_next <= '1';
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        end if;
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      end if;
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    end loop;
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  end if;
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--  s_debugo_pc_next <= pc;
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  r_next <= v;
224
end process;
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  -- Module Specific part
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229
--  mod_specific: process (r)
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--  begin  -- process mod_specific
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-- Multiplikation von 2 32 Bit Zahlen:
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--   mul_result <= (r.ifacereg(4)&r.ifacereg(5)) *(r.ifacereg(6)&r.ifacereg(7));
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235
--   end process mod_specific;
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-- Synchronous process 
239
  reg : process(clk)
240
  begin
241
    if rising_edge(clk) then
242
      if rstint = RST_ACT then
243
        r.ifacereg <= (others => (others => '0'));
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        do_trap <= '0';
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      else
246
        r <= r_next;
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        do_trap <= do_trap_next;
248
      end if;
249
    end if;
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  end process;
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  output : process(do_trap, debugo_rdata, watchpoint_act)
254
  begin
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    if r.ifacereg(CONFIGREG_CUST)(6 downto 3) = "0000" --No Traps during Single-Stepping
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        and r.ifacereg(STATUSREG)(STA_INT) = '0' --No Traps when Single-Step interrupt is active.
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        and (do_trap = '1' or watchpoint_act = '1') --Watchpoints can asynchronously request generation of Trap-instructions.                    
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    then
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      debugi_rdata <= "1110101100000000"; --TRAP0
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    else
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      debugi_rdata <= debugo_rdata;
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    end if;
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  end process;
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end behaviour;

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