OpenCores
URL https://opencores.org/ocsvn/scarts/scarts/trunk

Subversion Repositories scarts

[/] [scarts/] [trunk/] [processor/] [VHDL/] [scarts_core/] [brom.vhd] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 jlechner
-----------------------------------------------------------------------
2
-- This file is part of SCARTS.
3
-- 
4
-- SCARTS is free software: you can redistribute it and/or modify
5
-- it under the terms of the GNU General Public License as published by
6
-- the Free Software Foundation, either version 3 of the License, or
7
-- (at your option) any later version.
8
-- 
9
-- SCARTS is distributed in the hope that it will be useful,
10
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
-- GNU General Public License for more details.
13
-- 
14
-- You should have received a copy of the GNU General Public License
15
-- along with SCARTS.  If not, see <http://www.gnu.org/licenses/>.
16
-----------------------------------------------------------------------
17
 
18
 
19
library ieee;
20
use ieee.std_logic_1164.all;
21
use ieee.numeric_std.all;
22
 
23
use work.scarts_core_pkg.all;
24
use work.scarts_pkg.all;
25
 
26
entity scarts_brom is
27
  generic (
28
    CONF : scarts_conf_type);
29
  port (
30
    clk   : in  std_ulogic;
31
    hold  : in  std_ulogic;
32
    addr  : in  std_logic_vector(CONF.word_size-1 downto 0);
33
    data  : out INSTR);
34
end scarts_brom;
35
 
36
architecture behaviour of scarts_brom is
37
 
38
signal enable : std_ulogic;
39
signal data_int  :  INSTR;
40
 
41
begin
42
 
43
  enable <= not hold;
44
 
45
--  xilinx_gen : if (CONF.tech = XILINX) generate
46
 --   instr_rom_inst: xilinx_instr_rom
47
 --     port map (
48
 --       clk     => clk,
49
 --       enable  => enable,
50
 --       addr    => addr(15 downto 0),
51
 --      data    => data_int
52
 --     );
53
 -- end generate;
54
 
55
  altera_gen : if (CONF.tech = ALTERA) generate
56
    boot_rom_inst: altera_boot_rom
57
      generic map (
58
        CONF => CONF)
59
      port map (
60
        address => addr(15 downto 0),
61
        clken   => enable,
62
        clock   => clk,
63
        q       => data_int
64
      );
65
  end generate;
66
 
67
 
68
  -- little-endianness used for storing instructions in memory
69
  -- => swap bytes
70
  data(15 downto 8) <= data_int(7 downto 0);
71
  data(7 downto 0) <= data_int(15 downto 8);
72
 
73
end behaviour;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.