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[/] [scarts/] [trunk/] [processor/] [VHDL/] [scarts_core/] [brom.vhd] - Blame information for rev 7

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1 3 jlechner
-----------------------------------------------------------------------
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-- This file is part of SCARTS.
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-- 
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-- SCARTS is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- 
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-- SCARTS is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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-- GNU General Public License for more details.
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-- 
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-- You should have received a copy of the GNU General Public License
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-- along with SCARTS.  If not, see <http://www.gnu.org/licenses/>.
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.scarts_core_pkg.all;
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use work.scarts_pkg.all;
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entity scarts_brom is
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  generic (
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    CONF : scarts_conf_type);
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  port (
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    clk   : in  std_ulogic;
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    hold  : in  std_ulogic;
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    addr  : in  std_logic_vector(CONF.word_size-1 downto 0);
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    data  : out INSTR);
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end scarts_brom;
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architecture behaviour of scarts_brom is
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signal enable : std_ulogic;
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signal data_int  :  INSTR;
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begin
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  enable <= not hold;
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--  xilinx_gen : if (CONF.tech = XILINX) generate
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 --   instr_rom_inst: xilinx_instr_rom
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 --     port map (
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 --       clk     => clk,
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 --       enable  => enable,
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 --       addr    => addr(15 downto 0),
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 --      data    => data_int
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 --     );
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 -- end generate;
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  altera_gen : if (CONF.tech = ALTERA) generate
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    boot_rom_inst: altera_boot_rom
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      generic map (
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        CONF => CONF)
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      port map (
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        address => addr(15 downto 0),
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        clken   => enable,
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        clock   => clk,
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        q       => data_int
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      );
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  end generate;
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  -- little-endianness used for storing instructions in memory
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  -- => swap bytes
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  data(15 downto 8) <= data_int(7 downto 0);
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  data(7 downto 0) <= data_int(15 downto 8);
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end behaviour;

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