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[/] [scarts/] [trunk/] [processor/] [VHDL/] [scarts_core/] [byteram.vhd] - Blame information for rev 3

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1 3 jlechner
-----------------------------------------------------------------------
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-- This file is part of SCARTS.
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-- 
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-- SCARTS is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- 
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-- SCARTS is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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-- GNU General Public License for more details.
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-- 
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-- You should have received a copy of the GNU General Public License
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-- along with SCARTS.  If not, see <http://www.gnu.org/licenses/>.
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.scarts_core_pkg.all;
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use work.scarts_pkg.all;
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entity scarts_byteram is
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  generic (
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    CONF : scarts_conf_type);
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  port (
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    wclk        : in  std_ulogic;
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    rclk        : in  std_ulogic;
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    enable      : in  std_ulogic;
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    wdata       : in  std_logic_vector(7 downto 0);
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    waddr       : in  std_logic_vector((CONF.data_ram_size-3) downto 0);
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    wen         : in  std_ulogic;
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    raddr       : in  std_logic_vector((CONF.data_ram_size-3) downto 0);
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    rdata       : out std_logic_vector(7 downto 0)
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    );
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end scarts_byteram;
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architecture behaviour of scarts_byteram is
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-- FIXME (jl): is this correct?
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constant WORD_CNT : natural := 2**(CONF.data_ram_size - CONF.word_size/16);
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subtype WORD is std_logic_vector(7 downto 0);
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type ram_array is array (0 to WORD_CNT-1) of WORD;
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signal ram : ram_array := (others => (others => '0'));
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begin
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  process(wclk)
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  begin
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    if rising_edge(wclk) then
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      if (enable = '1') then
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        if wen = '1' then
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          ram(to_integer(unsigned(waddr))) <= wdata;
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        end if;
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      end if;
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    end if;
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  end process;
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  process(rclk)
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  begin
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    if rising_edge(rclk) then
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      if (enable = '1') then
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        rdata <= (others => '0');
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        rdata <= ram(to_integer(unsigned(raddr)));
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      end if;
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    end if;
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  end process;
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end behaviour;

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