OpenCores
URL https://opencores.org/ocsvn/scarts/scarts/trunk

Subversion Repositories scarts

[/] [scarts/] [trunk/] [processor/] [VHDL/] [scarts_core/] [iram.vhd] - Blame information for rev 25

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 jlechner
-----------------------------------------------------------------------
2
-- This file is part of SCARTS.
3
-- 
4
-- SCARTS is free software: you can redistribute it and/or modify
5
-- it under the terms of the GNU General Public License as published by
6
-- the Free Software Foundation, either version 3 of the License, or
7
-- (at your option) any later version.
8
-- 
9
-- SCARTS is distributed in the hope that it will be useful,
10
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
-- GNU General Public License for more details.
13
-- 
14
-- You should have received a copy of the GNU General Public License
15
-- along with SCARTS.  If not, see <http://www.gnu.org/licenses/>.
16
-----------------------------------------------------------------------
17
 
18
 
19
library ieee;
20
use ieee.std_logic_1164.all;
21
use ieee.numeric_std.all;
22
 
23
use work.scarts_core_pkg.all;
24
use work.scarts_pkg.all;
25
 
26
entity scarts_iram is
27
  generic (
28
    CONF : scarts_conf_type);
29
  port (
30
    wclk        : in  std_ulogic;
31
    rclk        : in  std_ulogic;
32
    hold        : in  std_ulogic;
33
 
34
    wdata       : in  INSTR;
35
    waddr       : in  std_logic_vector(CONF.instr_ram_size-1 downto 0);
36
    wen         : in  std_ulogic;
37
    raddr       : in  std_logic_vector(CONF.instr_ram_size-1 downto 0);
38
    rdata       : out INSTR);
39
end scarts_iram;
40
 
41
architecture behaviour of scarts_iram is
42
 
43
  constant NWORDS : integer  := 2**CONF.instr_ram_size;
44
  type ram_array is array (0 to NWORDS-1) of INSTR;
45
 
46
  signal ram : ram_array := (others => NOP);
47
  signal enable    : std_ulogic;
48
  signal data_int       : INSTR;
49
 
50
begin
51
 
52
  enable <= not hold;
53
 
54
  process(wclk)
55
  begin
56
    if rising_edge(wclk) then
57
      if (enable = '1') then
58
        if wen = '1' then
59
          ram(to_integer(unsigned(waddr))) <= wdata;
60
        end if;
61
      end if;
62
    end if;
63
  end process;
64
 
65
  process(rclk)
66
  begin
67
    if rising_edge(rclk) then
68
      if (enable = '1') then
69
        data_int <= (others => '0');
70
        data_int <= ram(to_integer(unsigned(raddr)));
71
      end if;
72
    end if;
73
  end process;
74
 
75
  -- little-endianness used for storing instructions in memory
76
  -- => swap bytes
77
  rdata(15 downto 8) <= data_int(7 downto 0);
78
  rdata(7 downto 0) <= data_int(15 downto 8);
79
 
80
end behaviour;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.