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[/] [scarts/] [trunk/] [processor/] [VHDL/] [scarts_core/] [prog.vhd] - Blame information for rev 17

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1 3 jlechner 
-----------------------------------------------------------------------
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-- This file is part of SCARTS.
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--
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-- SCARTS is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- SCARTS is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with SCARTS.  If not, see <http://www.gnu.org/licenses/>.
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-----------------------------------------------------------------------
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18 
 
19 
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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23 
use work.scarts_core_pkg.all;
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use work.scarts_pkg.all;
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entity scarts_prog is
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  generic (
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    CONF : scarts_conf_type);
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  port (
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    clk     : in  std_ulogic;
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    extrst  : in  std_ulogic;
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    progrst : out std_ulogic;
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    hold    : in  std_ulogic;
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    extsel  : in  std_ulogic;
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    exti    : in  module_in_type;
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    exto    : out module_out_type;
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    instrsrc    : out std_ulogic;
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    prupdate    : out std_ulogic;
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    praddr      : out std_logic_vector(CONF.instr_ram_size-1 downto 0);
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    prdata      : out INSTR);
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end scarts_prog;
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architecture behaviour of scarts_prog is
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constant WORD_W : natural := CONF.word_size;
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subtype WORD is std_logic_vector(WORD_W-1 downto 0);
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subtype BYTE is std_logic_vector(7 downto 0);
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type register_set is array (0 to 9) of BYTE;
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constant STATUSREG_CUST : integer := 1;
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constant CONFIGREG_CUST : integer := 3;
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constant PR_ADDR_0 :integer := 4;
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constant PR_ADDR_1 :integer := 5;
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constant PR_ADDR_2 :integer := 6;
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constant PR_ADDR_3 :integer := 7;
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constant PR_DATA_0 :integer := 8;
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constant PR_DATA_1 :integer := 9;
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64 
 
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type reg_type is record
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  ifacereg  : register_set;
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end record;
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69 
 
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signal r_next : reg_type;
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signal r : reg_type :=
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  (
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    ifacereg => (others => (others => '0'))
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  );
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begin
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  comb : process(r, extrst, exti, extsel)
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  variable v : reg_type;
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  variable pr_addr_v, pr_addr_new_v : WORD;
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82 
  begin
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    v := r;
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    --schreiben
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    if ((extsel = '1') and (exti.write_en = '1')) then
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      case exti.addr(4 downto 2) is
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        when "000" =>
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          if ((exti.byte_en(0) = '1') or (exti.byte_en(1) = '1')) then
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            v.ifacereg(STATUSREG)(STA_INT) := '1';
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            v.ifacereg(CONFIGREG)(CONF_INTA) :='0';
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          else
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            if ((exti.byte_en(2) = '1')) then
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              v.ifacereg(2) := exti.data(23 downto 16);
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            end if;
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            if ((exti.byte_en(3) = '1')) then
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              v.ifacereg(3) := exti.data(31 downto 24);
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            end if;
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          end if;
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        when "001" =>
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          if ((exti.byte_en(0) = '1')) then
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            v.ifacereg(4) := exti.data(7 downto 0);
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          end if;
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          if ((exti.byte_en(1) = '1')) then
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            v.ifacereg(5) := exti.data(15 downto 8);
106 
          end if;
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          if ((exti.byte_en(2) = '1')) then
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            if CONF.word_size = 32 then
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              v.ifacereg(6) := exti.data(23 downto 16);
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            end if;
111 
          end if;
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          if ((exti.byte_en(3) = '1')) then
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            if CONF.word_size = 32 then
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              v.ifacereg(7) := exti.data(31 downto 24);
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            end if;
116 
          end if;
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        when "010" =>
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          if ((exti.byte_en(0) = '1')) then
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            v.ifacereg(8) := exti.data(7 downto 0);
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          end if;
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          if ((exti.byte_en(1) = '1')) then
122 
            v.ifacereg(9) := exti.data(15 downto 8);
123 
          end if;
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        when others =>
125 
          null;
126 
      end case;
127 
    end if;
128 
 
129 
 
130 
    --auslesen
131 
    if CONF.word_size = 32 then
132 
    exto.data <= (others => '0');
133 
    if ((extsel = '1') and (exti.write_en = '0')) then
134 
      case exti.addr(4 downto 2) is
135 
        when "000" =>
136 
          exto.data <= r.ifacereg(3) & r.ifacereg(2) & r.ifacereg(1) & r.ifacereg(0);
137 
        when "001" =>
138 
          if (r.ifacereg(CONFIGREG)(CONF_ID) = '1') then
139 
            exto.data <= MODULE_VER & MODULE_ID;
140 
          else
141 
            if CONF.word_size = 32 then
142 
              exto.data <= r.ifacereg(7) & r.ifacereg(6) & r.ifacereg(5) & r.ifacereg(4);
143 
            else
144 
              exto.data <= "00000000"    & "00000000"    & r.ifacereg(5) & r.ifacereg(4);
145 
            end if;
146 
          end if;
147 
        when "010" =>
148 
          exto.data <= "00000000" & "00000000" & r.ifacereg(9) & r.ifacereg(8);
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        when others =>
150 
          null;
151 
      end case;
152 
    end if;
153 
 
154 
      exto.data <= (others => '0');
155 
      if ((extsel = '1') and (exti.write_en = '0')) then
156 
        case exti.addr(4 downto 1) is
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          when "0000" =>
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            exto.data(15 downto 0) <= r.ifacereg(1) & r.ifacereg(0);
159 
          when "0001" =>
160 
            exto.data(15 downto 0) <= r.ifacereg(3) & r.ifacereg(2);
161 
          when "0010" =>
162 
            if (r.ifacereg(CONFIGREG)(CONF_ID) = '1') then
163 
              exto.data(15 downto 0) <= MODULE_ID;
164 
            else
165 
              exto.data(15 downto 0) <= r.ifacereg(5) & r.ifacereg(4);
166 
            end if;
167 
          when "0011" =>
168 
            if (r.ifacereg(CONFIGREG)(CONF_ID) = '1') then
169 
              exto.data(15 downto 0) <= MODULE_VER;
170 
            else
171 
              exto.data(15 downto 0) <= r.ifacereg(7) & r.ifacereg(6);
172 
            end if;
173 
          when "0100" =>
174 
            exto.data(15 downto 0) <= r.ifacereg(9) & r.ifacereg(8);
175 
          when others =>
176 
            null;
177 
        end case;
178 
      end if;
179 
    end if;
180 
 
181 
    --berechnen der neuen status flags
182 
    v.ifacereg(STATUSREG)(STA_LOOR) := r.ifacereg(CONFIGREG)(CONF_LOOW);
183 
    v.ifacereg(STATUSREG)(STA_FSS) := '0';
184 
    v.ifacereg(STATUSREG)(STA_RESH) := '0';
185 
    v.ifacereg(STATUSREG)(STA_RESL) := '0';
186 
    v.ifacereg(STATUSREG)(STA_BUSY) := '0';
187 
    v.ifacereg(STATUSREG)(STA_ERR) := '0';
188 
    v.ifacereg(STATUSREG)(STA_RDY) := '1';
189 
  --  v.ifacereg(STATUSREG)(STA_INT) := '0';
190 
 
191 
--    if exti.extaddr(2) = '1' then
192 
--      v.ifacereg(STATUSREG)(STA_ERR) := '1';
193 
--      v.ifacereg(STATUSREG)(STA_INT) := '1';
194 
--      v.ifacereg(CONFIGREG)(CONF_INTA):= '0';
195 
--    end if;
196 
 
197 
    if r.ifacereg(STATUSREG)(STA_INT) = '1' and r.ifacereg(CONFIGREG)(CONF_INTA) ='1' then
198 
      v.ifacereg(STATUSREG)(STA_INT) := '0';
199 
    end if;
200 
    exto.intreq <= r.ifacereg(STATUSREG)(STA_INT);
201 
 
202 
 
203 
    --module specific part
204 
    pr_addr_v(7 downto 0) := r.ifacereg(PR_ADDR_0);
205 
    pr_addr_v(15 downto 8) := r.ifacereg(PR_ADDR_1);
206 
    if CONF.word_size = 32 then
207 
      pr_addr_v(WORD_W-9 downto WORD_W-16) := r.ifacereg(PR_ADDR_2);
208 
      pr_addr_v(WORD_W-1 downto WORD_W-8) := r.ifacereg(PR_ADDR_3);
209 
    end if;
210 
          pr_addr_new_v := pr_addr_v;
211 
 
212 
    if r.ifacereg(CONFIGREG_CUST)(CONF_PREXE) = PR_UPDATE then
213 
      v.ifacereg(CONFIGREG_CUST)(CONF_PREXE) := not PR_UPDATE;
214 
      pr_addr_new_v := std_logic_vector(unsigned(pr_addr_v) + 1);
215 
    end if;
216 
 
217 
    v.ifacereg(PR_ADDR_0) :=   pr_addr_new_v(7 downto 0);
218 
          v.ifacereg(PR_ADDR_1) :=   pr_addr_new_v(15 downto 8);
219 
    if CONF.word_size = 32 then
220 
      v.ifacereg(PR_ADDR_2) :=   pr_addr_new_v(WORD_W-9 downto WORD_W-16);
221 
      v.ifacereg(PR_ADDR_3) :=   pr_addr_new_v(WORD_W-1 downto WORD_W-8);
222 
    end if;
223 
 
224 
    --soft- und hard-reset vereinen
225 
    progrst <= not RST_ACT;
226 
    if extrst = RST_ACT or r.ifacereg(CONFIGREG_CUST)(CONF_CLR) = '1' then
227 
      progrst <= RST_ACT;
228 
      v.ifacereg(CONFIGREG_CUST)(CONF_CLR) := '0';
229 
    end if;
230 
 
231 
    -- output
232 
    instrsrc <= r.ifacereg(CONFIGREG_CUST)(CONF_INSTRSRC);
233 
    prupdate <= r.ifacereg(CONFIGREG_CUST)(CONF_PREXE);
234 
 
235 
    praddr <= pr_addr_v(CONF.instr_ram_size-1 downto 0);
236 
 
237 
    prdata(7 downto 0) <= r.ifacereg(PR_DATA_1);
238 
    prdata(15 downto 8) <= r.ifacereg(PR_DATA_0);
239 
 
240 
    r_next <= v;
241 
  end process;
242 
 
243 
  reg : process(clk)--, extrst)
244 
  begin
245 
    if rising_edge(clk) then
246 
      if extrst = RST_ACT then
247 
        r.ifacereg <= (others => (others => '0'));
248 
      else
249 
        if (hold = not HOLD_ACT) then
250 
          r <= r_next;
251 
        end if;
252 
      end if;
253 
    end if;
254 
  end process;
255 
 
256 
end behaviour;

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