OpenCores
URL https://opencores.org/ocsvn/scarts/scarts/trunk

Subversion Repositories scarts

[/] [scarts/] [trunk/] [processor/] [VHDL/] [scarts_core/] [prog.vhd] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 jlechner 
-----------------------------------------------------------------------
2 
-- This file is part of SCARTS.
3 
--
4 
-- SCARTS is free software: you can redistribute it and/or modify
5 
-- it under the terms of the GNU General Public License as published by
6 
-- the Free Software Foundation, either version 3 of the License, or
7 
-- (at your option) any later version.
8 
--
9 
-- SCARTS is distributed in the hope that it will be useful,
10 
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 
-- GNU General Public License for more details.
13 
--
14 
-- You should have received a copy of the GNU General Public License
15 
-- along with SCARTS.  If not, see <http://www.gnu.org/licenses/>.
16 
-----------------------------------------------------------------------
17 
 
18 
 
19 
library ieee;
20 
use ieee.std_logic_1164.all;
21 
use ieee.numeric_std.all;
22 
 
23 
use work.scarts_core_pkg.all;
24 
use work.scarts_pkg.all;
25 
 
26 
entity scarts_prog is
27 
  generic (
28 
    CONF : scarts_conf_type);
29 
  port (
30 
    clk     : in  std_ulogic;
31 
    extrst  : in  std_ulogic;
32 
    progrst : out std_ulogic;
33 
    hold    : in  std_ulogic;
34 
    extsel  : in  std_ulogic;
35 
    exti    : in  module_in_type;
36 
    exto    : out module_out_type;
37 
 
38 
    instrsrc    : out std_ulogic;
39 
    prupdate    : out std_ulogic;
40 
    praddr      : out std_logic_vector(CONF.instr_ram_size-1 downto 0);
41 
    prdata      : out INSTR);
42 
end scarts_prog;
43 
 
44 
architecture behaviour of scarts_prog is
45 
 
46 
constant WORD_W : natural := CONF.word_size;
47 
subtype WORD is std_logic_vector(WORD_W-1 downto 0);
48 
 
49 
subtype BYTE is std_logic_vector(7 downto 0);
50 
type register_set is array (0 to 9) of BYTE;
51 
 
52 
 
53 
constant STATUSREG_CUST : integer := 1;
54 
constant CONFIGREG_CUST : integer := 3;
55 
 
56 
constant PR_ADDR_0 :integer := 4;
57 
constant PR_ADDR_1 :integer := 5;
58 
constant PR_ADDR_2 :integer := 6;
59 
constant PR_ADDR_3 :integer := 7;
60 
 
61 
constant PR_DATA_0 :integer := 8;
62 
constant PR_DATA_1 :integer := 9;
63 
 
64 
 
65 
type reg_type is record
66 
  ifacereg  : register_set;
67 
end record;
68 
 
69 
 
70 
signal r_next : reg_type;
71 
signal r : reg_type :=
72 
  (
73 
    ifacereg => (others => (others => '0'))
74 
  );
75 
 
76 
begin
77 
 
78 
  comb : process(r, extrst, exti, extsel)
79 
  variable v : reg_type;
80 
  variable pr_addr_v, pr_addr_new_v : WORD;
81 
 
82 
  begin
83 
    v := r;
84 
 
85 
    --schreiben
86 
    if ((extsel = '1') and (exti.write_en = '1')) then
87 
      case exti.addr(4 downto 2) is
88 
        when "000" =>
89 
          if ((exti.byte_en(0) = '1') or (exti.byte_en(1) = '1')) then
90 
            v.ifacereg(STATUSREG)(STA_INT) := '1';
91 
            v.ifacereg(CONFIGREG)(CONF_INTA) :='0';
92 
          else
93 
            if ((exti.byte_en(2) = '1')) then
94 
              v.ifacereg(2) := exti.data(23 downto 16);
95 
            end if;
96 
            if ((exti.byte_en(3) = '1')) then
97 
              v.ifacereg(3) := exti.data(31 downto 24);
98 
            end if;
99 
          end if;
100 
        when "001" =>
101 
          if ((exti.byte_en(0) = '1')) then
102 
            v.ifacereg(4) := exti.data(7 downto 0);
103 
          end if;
104 
          if ((exti.byte_en(1) = '1')) then
105 
            v.ifacereg(5) := exti.data(15 downto 8);
106 
          end if;
107 
          if ((exti.byte_en(2) = '1')) then
108 
            if CONF.word_size = 32 then
109 
              v.ifacereg(6) := exti.data(23 downto 16);
110 
            end if;
111 
          end if;
112 
          if ((exti.byte_en(3) = '1')) then
113 
            if CONF.word_size = 32 then
114 
              v.ifacereg(7) := exti.data(31 downto 24);
115 
            end if;
116 
          end if;
117 
        when "010" =>
118 
          if ((exti.byte_en(0) = '1')) then
119 
            v.ifacereg(8) := exti.data(7 downto 0);
120 
          end if;
121 
          if ((exti.byte_en(1) = '1')) then
122 
            v.ifacereg(9) := exti.data(15 downto 8);
123 
          end if;
124 
        when others =>
125 
          null;
126 
      end case;
127 
    end if;
128 
 
129 
 
130 
    --auslesen
131 
    if CONF.word_size = 32 then
132 
    exto.data <= (others => '0');
133 
    if ((extsel = '1') and (exti.write_en = '0')) then
134 
      case exti.addr(4 downto 2) is
135 
        when "000" =>
136 
          exto.data <= r.ifacereg(3) & r.ifacereg(2) & r.ifacereg(1) & r.ifacereg(0);
137 
        when "001" =>
138 
          if (r.ifacereg(CONFIGREG)(CONF_ID) = '1') then
139 
            exto.data <= MODULE_VER & MODULE_ID;
140 
          else
141 
            if CONF.word_size = 32 then
142 
              exto.data <= r.ifacereg(7) & r.ifacereg(6) & r.ifacereg(5) & r.ifacereg(4);
143 
            else
144 
              exto.data <= "00000000"    & "00000000"    & r.ifacereg(5) & r.ifacereg(4);
145 
            end if;
146 
          end if;
147 
        when "010" =>
148 
          exto.data <= "00000000" & "00000000" & r.ifacereg(9) & r.ifacereg(8);
149 
        when others =>
150 
          null;
151 
      end case;
152 
    end if;
153 
 
154 
      exto.data <= (others => '0');
155 
      if ((extsel = '1') and (exti.write_en = '0')) then
156 
        case exti.addr(4 downto 1) is
157 
          when "0000" =>
158 
            exto.data(15 downto 0) <= r.ifacereg(1) & r.ifacereg(0);
159 
          when "0001" =>
160 
            exto.data(15 downto 0) <= r.ifacereg(3) & r.ifacereg(2);
161 
          when "0010" =>
162 
            if (r.ifacereg(CONFIGREG)(CONF_ID) = '1') then
163 
              exto.data(15 downto 0) <= MODULE_ID;
164 
            else
165 
              exto.data(15 downto 0) <= r.ifacereg(5) & r.ifacereg(4);
166 
            end if;
167 
          when "0011" =>
168 
            if (r.ifacereg(CONFIGREG)(CONF_ID) = '1') then
169 
              exto.data(15 downto 0) <= MODULE_VER;
170 
            else
171 
              exto.data(15 downto 0) <= r.ifacereg(7) & r.ifacereg(6);
172 
            end if;
173 
          when "0100" =>
174 
            exto.data(15 downto 0) <= r.ifacereg(9) & r.ifacereg(8);
175 
          when others =>
176 
            null;
177 
        end case;
178 
      end if;
179 
    end if;
180 
 
181 
    --berechnen der neuen status flags
182 
    v.ifacereg(STATUSREG)(STA_LOOR) := r.ifacereg(CONFIGREG)(CONF_LOOW);
183 
    v.ifacereg(STATUSREG)(STA_FSS) := '0';
184 
    v.ifacereg(STATUSREG)(STA_RESH) := '0';
185 
    v.ifacereg(STATUSREG)(STA_RESL) := '0';
186 
    v.ifacereg(STATUSREG)(STA_BUSY) := '0';
187 
    v.ifacereg(STATUSREG)(STA_ERR) := '0';
188 
    v.ifacereg(STATUSREG)(STA_RDY) := '1';
189 
  --  v.ifacereg(STATUSREG)(STA_INT) := '0';
190 
 
191 
--    if exti.extaddr(2) = '1' then
192 
--      v.ifacereg(STATUSREG)(STA_ERR) := '1';
193 
--      v.ifacereg(STATUSREG)(STA_INT) := '1';
194 
--      v.ifacereg(CONFIGREG)(CONF_INTA):= '0';
195 
--    end if;
196 
 
197 
    if r.ifacereg(STATUSREG)(STA_INT) = '1' and r.ifacereg(CONFIGREG)(CONF_INTA) ='1' then
198 
      v.ifacereg(STATUSREG)(STA_INT) := '0';
199 
    end if;
200 
    exto.intreq <= r.ifacereg(STATUSREG)(STA_INT);
201 
 
202 
 
203 
    --module specific part
204 
    pr_addr_v(7 downto 0) := r.ifacereg(PR_ADDR_0);
205 
    pr_addr_v(15 downto 8) := r.ifacereg(PR_ADDR_1);
206 
    if CONF.word_size = 32 then
207 
      pr_addr_v(WORD_W-9 downto WORD_W-16) := r.ifacereg(PR_ADDR_2);
208 
      pr_addr_v(WORD_W-1 downto WORD_W-8) := r.ifacereg(PR_ADDR_3);
209 
    end if;
210 
          pr_addr_new_v := pr_addr_v;
211 
 
212 
    if r.ifacereg(CONFIGREG_CUST)(CONF_PREXE) = PR_UPDATE then
213 
      v.ifacereg(CONFIGREG_CUST)(CONF_PREXE) := not PR_UPDATE;
214 
      pr_addr_new_v := std_logic_vector(unsigned(pr_addr_v) + 1);
215 
    end if;
216 
 
217 
    v.ifacereg(PR_ADDR_0) :=   pr_addr_new_v(7 downto 0);
218 
          v.ifacereg(PR_ADDR_1) :=   pr_addr_new_v(15 downto 8);
219 
    if CONF.word_size = 32 then
220 
      v.ifacereg(PR_ADDR_2) :=   pr_addr_new_v(WORD_W-9 downto WORD_W-16);
221 
      v.ifacereg(PR_ADDR_3) :=   pr_addr_new_v(WORD_W-1 downto WORD_W-8);
222 
    end if;
223 
 
224 
    --soft- und hard-reset vereinen
225 
    progrst <= not RST_ACT;
226 
    if extrst = RST_ACT or r.ifacereg(CONFIGREG_CUST)(CONF_CLR) = '1' then
227 
      progrst <= RST_ACT;
228 
      v.ifacereg(CONFIGREG_CUST)(CONF_CLR) := '0';
229 
    end if;
230 
 
231 
    -- output
232 
    instrsrc <= r.ifacereg(CONFIGREG_CUST)(CONF_INSTRSRC);
233 
    prupdate <= r.ifacereg(CONFIGREG_CUST)(CONF_PREXE);
234 
 
235 
    praddr <= pr_addr_v(CONF.instr_ram_size-1 downto 0);
236 
 
237 
    prdata(7 downto 0) <= r.ifacereg(PR_DATA_1);
238 
    prdata(15 downto 8) <= r.ifacereg(PR_DATA_0);
239 
 
240 
    r_next <= v;
241 
  end process;
242 
 
243 
  reg : process(clk)--, extrst)
244 
  begin
245 
    if rising_edge(clk) then
246 
      if extrst = RST_ACT then
247 
        r.ifacereg <= (others => (others => '0'));
248 
      else
249 
        if (hold = not HOLD_ACT) then
250 
          r <= r_next;
251 
        end if;
252 
      end if;
253 
    end if;
254 
  end process;
255 
 
256 
end behaviour;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.