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[/] [scarts/] [trunk/] [processor/] [VHDL/] [scarts_core/] [rs232.vhd] - Blame information for rev 3

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1 3 jlechner 
-----------------------------------------------------------------------
2 
-- This file is part of SCARTS.
3 
--
4 
-- SCARTS is free software: you can redistribute it and/or modify
5 
-- it under the terms of the GNU General Public License as published by
6 
-- the Free Software Foundation, either version 3 of the License, or
7 
-- (at your option) any later version.
8 
--
9 
-- SCARTS is distributed in the hope that it will be useful,
10 
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 
-- GNU General Public License for more details.
13 
--
14 
-- You should have received a copy of the GNU General Public License
15 
-- along with SCARTS.  If not, see <http://www.gnu.org/licenses/>.
16 
-----------------------------------------------------------------------
17 
 
18 
 
19 
-------------------------------------------------------------------------------
20 
-- Title      : Extension Module: miniUART
21 
-- Project    : HW/SW-Codesign
22 
-------------------------------------------------------------------------------
23 
-- File       : ext_miniUART.vhd
24 
-- Author     : Roman Seiger
25 
-- Company    : TU Wien - Institut für Technische Informatik
26 
-- Created    : 2005-03-10
27 
-- Last update: 2011-03-16
28 
-------------------------------------------------------------------------------
29 
 
30 
-- TODO: Herstellernummer
31 
 
32 
----------------------------------------------------------------------------------
33 
-- LIBRARY
34 
----------------------------------------------------------------------------------
35 
 
36 
LIBRARY IEEE;
37 
USE IEEE.std_logic_1164.all;
38 
USE IEEE.numeric_std.all;
39 
 
40 
use work.scarts_core_pkg.all;
41 
use work.scarts_pkg.all;
42 
 
43 
----------------------------------------------------------------------------------
44 
-- ENTITY
45 
----------------------------------------------------------------------------------
46 
 
47 
ENTITY ext_miniUART IS
48 
        PORT(   ---------------------------------------------------------------
49 
                -- Generic Ports
50 
                ---------------------------------------------------------------
51 
                clk           : IN  std_logic;
52 
                extsel        : in  std_logic;
53 
                exti          : in  module_in_type;
54 
                exto          : out module_out_type;
55 
                ---------------------------------------------------------------
56 
                -- Module Specific Ports
57 
                ---------------------------------------------------------------
58 
                RxD           : IN std_logic;  -- Empfangsleitung
59 
                TxD           : OUT std_logic
60 
                );
61 
END ext_miniUART;
62 
 
63 
 
64 
----------------------------------------------------------------------------------
65 
-- ARCHITECTURE
66 
----------------------------------------------------------------------------------
67 
ARCHITECTURE behaviour OF ext_miniUART IS
68 
 
69 
------------------------------------------------------------------------------
70 
-- Definition der Constanten für Module Type und versionsnummer
71 
-------------------------------------------------------------------------------
72 
-- ID für miniUART definieren
73 
  constant MOD_TYPE     : std_logic_vector(15 downto 0):="0000000100000001";
74 
  constant MOD_VERSION  : std_logic_vector(15 downto 0):="0000000000000000";
75 
 
76 
 
77 
-------------------------------------------------------------------------------
78 
-- Definieren eines Types "ext_register_set" : Array vom 8 Registern die
79 
-- jeweils 16 Bit breit sind => Register der Module Interfaces
80 
-------------------------------------------------------------------------------
81 
  subtype ext_register is std_logic_vector(7 downto 0);
82 
  type    ext_register_set is array (0 to 9) of ext_register;
83 
  signal  ExtReg,ExtReg_next         : ext_register_set;
84 
 
85 
-------------------------------------------------------------------------------
86 
--  Interne Signale, siehe Programm-Code
87 
-------------------------------------------------------------------------------
88 
  signal ExtReset                        : std_logic;  -- reset oder SRes
89 
--  signal Ena                             : std_logic;  -- Modul angesprochen
90 
  signal IntAckClrNxt                    : std_logic;
91 
  --signal WriteDataNxt                    : std_logic_vector(DATA_W-1 downto 0);
92 
  -- ganzes Statusregister überschreiben!
93 
--  signal StatusNxt                       : std_logic_vector((DATA_W/2)-1 downto 0);
94 
  signal StatusNxt                       : std_logic_vector(DATA_W-1 downto 0);
95 
--  signal MsgNxt                          : std_logic_vector(DATA_W-1 downto 0);
96 
--  signal CmdNxt                          : std_logic_vector(DATA_W-1 downto 0);
97 
  signal UBRS                            : std_logic_vector(DATA_W-1 downto 0);
98 
 
99 
--  signal parity : std_logic;            -- für Parityberechnung
100 
  signal newmessage : std_logic;        -- neue Nachricht ins Messageregister geschrieben?
101 
  signal messageread : std_logic;       -- empfangene Nachricht abgeholt?
102 
  signal statusread : std_logic;        -- Status gelesen? (für Eventflag)
103 
  signal old_statusread : std_logic;
104 
 
105 
  --signal MINIUART_BADDR                  : std_logic_vector(DATA_W-1 downto 3);
106 
 
107 
-------------------------------------------------------------------------------
108 
-- Verbindungssignale
109 
-------------------------------------------------------------------------------
110 
  -- Transmitter
111 
  signal ParBit : std_logic;            -- berechnetes Paritybit für Transmitter
112 
 
113 
  -- Busdriver
114 
  signal OutD : std_logic;              -- Output disable
115 
 
116 
  -- UARTCtrl
117 
  signal ParErr : std_logic;          -- Parity Error
118 
  signal FrameErr : std_logic;        -- Frame Error (Transmission Error)
119 
  signal Data_r : Data_type;            -- empfangene Daten
120 
  signal RBR : std_logic;               -- Receive Buffer Ready
121 
  signal TBR : std_logic;               -- Transmit Buffer Ready
122 
  signal event : std_logic;             -- event occured?
123 
 
124 
  -- UARTCtrl <=> receiver
125 
  signal Data_r2c : Data_type;
126 
  signal Data_c2t : Data_type;
127 
  signal ParBit_r2c : std_logic;
128 
  signal FrameErr_r2c : std_logic;
129 
  signal RecComp_r2c : std_logic;
130 
  signal RecBusy_r2c : std_logic;
131 
  signal EnaRec_c2r : std_logic;
132 
 
133 
  -- UARTCtrl <=> transmitter
134 
  signal TransComp_t2c : std_logic;
135 
 
136 
  -- UARTcontrol <=> BRG
137 
  signal StartTrans_c2brg : std_logic;
138 
 
139 
  -- transmitter <=> BRG
140 
  signal tp_brg2t : std_logic;
141 
 
142 
  -- transmitter <=> busdriver
143 
  signal TransEna_t2bd : std_logic;
144 
  signal TxD_t2bd : std_logic;
145 
 
146 
  -- receiver <=> BRG
147 
  signal rp_brg2r : std_logic;
148 
  signal StartRecPulse_r2brg : std_logic;
149 
 
150 
  -- receiver <=> busdriver
151 
  signal RecEna_r2bd : std_logic;
152 
  signal RxD_bd2r : std_logic;
153 
 
154 
-------------------------------------------------------------------------------
155 
-- begin architecture
156 
-------------------------------------------------------------------------------
157 
  begin  -- behaviour
158 
 
159 
-------------------------------------------------------------------------------
160 
-- Port mapping der Komponenten
161 
-------------------------------------------------------------------------------
162 
    -- miniUART_control
163 
    miniUART_control_unit : miniUART_control
164 
      port map (
165 
        clk => clk,
166 
        reset => ExtReset,
167 
        ParEna => ExtReg(EXTUARTCONF)(EXTCONF_PARENA),
168 
        Odd => ExtReg(EXTUARTCONF)(EXTCONF_PARODD),
169 
        AsA => ExtReg(EXTCMD)(EXTCMD_ASA_H downto EXTCMD_ASA_L),
170 
        EvS => ExtReg(EXTCMD)(EXTCMD_EVS_H downto EXTCMD_EVS_L),
171 
        Data_r => Data_r2c,
172 
        ParBit_r => ParBit_r2c,
173 
        FrameErr => FrameErr_r2c,
174 
        RecComp => RecComp_r2c,
175 
        RecBusy => RecBusy_r2c,
176 
        TransComp => TransComp_t2c,
177 
        EnaRec => EnaRec_c2r,
178 
        Data_r_out => Data_r,
179 
        FrameErr_out => FrameErr,
180 
        ParityErr => ParErr,
181 
        RBR => RBR,
182 
        StartTrans => StartTrans_c2brg,
183 
        TBR => TBR,
184 
        event => event
185 
        );
186 
 
187 
                Data_c2t(7 downto 0) <= ExtReg(MSGREG_LOW);
188 
                Data_c2t(15 downto 8) <= ExtReg(MSGREG_HIGH);
189 
 
190 
    -- miniUART_transmitter
191 
    miniUART_transmitter_unit : miniUART_transmitter
192 
      port map (
193 
        clk => clk,
194 
        reset => ExtReset,
195 
        MsgLength => ExtReg(EXTUARTCONF)(EXTCONF_MSGL_H downto EXTCONF_MSGL_L),
196 
        Stop2 => ExtReg(EXTUARTCONF)(EXTCONF_STOP),
197 
        ParEna => ExtReg(EXTUARTCONF)(EXTCONF_PARENA),
198 
        ParBit => ParBit,
199 
        Data => Data_c2t,
200 
        tp => tp_brg2t,
201 
        TransEna => TransEna_t2bd,
202 
        TrComp => TransComp_t2c,
203 
        TxD => TxD_t2bd
204 
        );
205 
 
206 
    -- miniUART_receiver
207 
    miniUART_receiver_unit : miniUART_receiver
208 
      port map (
209 
        clk => clk,
210 
                reset => ExtReset,
211 
        enable => EnaRec_c2r,
212 
        MsgLength => ExtReg(EXTUARTCONF)(EXTCONF_MSGL_H downto EXTCONF_MSGL_L),
213 
        Stop2 => ExtReg(EXTUARTCONF)(EXTCONF_STOP),
214 
        ParEna => ExtReg(EXTUARTCONF)(EXTCONF_PARENA),
215 
        rp => rp_brg2r,
216 
        RxD => RxD_bd2r,
217 
        Data => Data_r2c,
218 
        ParBit => ParBit_r2c,
219 
        RecEna => RecEna_r2bd,
220 
        StartRecPulse => StartRecPulse_r2brg,
221 
        busy => RecBusy_r2c,
222 
        RecComplete => RecComp_r2c,
223 
        FrameErr => FrameErr_r2c
224 
        );
225 
 
226 
     UBRS(7 downto 0)  <= ExtReg(UBRSREG_LOW);
227 
     UBRS(15 downto 8) <= ExtReg(UBRSREG_HIGH);
228 
 
229 
    -- miniUART_BRG
230 
    miniUART_BRG_unit : miniUART_BRG
231 
      port map (
232 
        clk => clk,
233 
                reset => ExtReset,
234 
        StartTrans => StartTrans_c2brg,
235 
        StartRec => StartRecPulse_r2brg,
236 
        UBRS => UBRS,--ExtReg(UBRSREG),
237 
        tp => tp_brg2t,
238 
        rp => rp_brg2r
239 
        );
240 
 
241 
 
242 
    -- miniUART_busdriver
243 
    miniUART_busdriver_unit : miniUART_busdriver
244 
      port map (
245 
        clk => clk,
246 
                reset => ExtReset,
247 
        OutD => OutD,
248 
        TransEna => TransEna_t2bd,
249 
        RecEna => RecEna_r2bd,
250 
        Data_t => TxD_t2bd,
251 
        Data_r => RxD_bd2r,
252 
        TxD => TxD,
253 
        RxD => RxD
254 
        );
255 
 
256 
 
257 
-------------------------------------------------------------------------------
258 
-- Synchroner Prozess:
259 
-- Bei einem Reset werden alle Register mit Null initialisiert.
260 
-- Anschliessend werden mit jeder steigenden Flanke die neuen Werte in das
261 
-- Register geschrieben.
262 
-- Zu beachten ist dabei die Reigenfolge: StatusNxt wird
263 
-- als letztes zugewiesen - daher wird in jedem Fall das Status Register mit
264 
-- diesem Wert beschreiben, auch wenn man von aussen versucht  dieses zu
265 
-- überschreiben  -> read-only Funktion  (nur die unteren 8 Bits). Beim
266 
-- Config-Register ist es genau umgekehrt - dadurch kann man das INTA-Bit vom
267 
-- Prozessor aus überschreiben..
268 
-------------------------------------------------------------------------------
269 
    SYNC_SM: process (clk, ExtReset)
270 
    begin
271 
 
272 
      if ExtReset = RST_ACT then
273 
        for i in 0 to 9 loop
274 
          ExtReg(i) <= (others => '0');
275 
        end loop;  -- i
276 
        old_statusread <= '0';
277 
      elsif clk'event and clk = '1' then
278 
        ExtReg <= ExtReg_next;
279 
 
280 
        ExtReg(STATUSREG) <= StatusNxt(7 downto 0);
281 
        ExtReg(STATUSREG_CUST) <= StatusNxt(15 downto 8);
282 
        old_statusread <= statusread;
283 
 
284 
      end if;
285 
    end process SYNC_SM;
286 
 
287 
 
288 
 
289 
 
290 
-------------------------------------------------------------------------------
291 
-- Schreiben in die Register:
292 
-- Defaultmässig wird der ältere Wert beibehalten
293 
-------------------------------------------------------------------------------
294 
    WRITE_REG: process (exti, ExtReg, RBR, TBR,  Data_r, extsel, IntAckClrNxt)--(ExtAddr, Data2Ext, ExtWr, Ena, ExtReg) --DE, AccViol)
295 
    begin
296 
 
297 
      -- Defaultwert
298 
      ExtReg_next <= ExtReg;
299 
      ExtReg_next(CONFIGREG)(CONF_INTA)  <= IntAckClrNxt;
300 
      --WriteDataNxt <=  ExtReg(conv_integer(unsigned(exti.ExtAddr)));
301 
      newmessage <= '0';
302 
      if RBR = RB_READY then
303 
        ExtReg_next(MSGREG_LOW)   <= Data_r(7 downto 0);       -- empfangene Nachricht übernehmen
304 
        ExtReg_next(MSGREG_HIGH) <= Data_r(15 downto 8);
305 
      end if;
306 
 
307 
      if TBR = TB_READY then
308 
        if ExtReg(EXTCMD)(EXTCMD_ASA_H downto EXTCMD_ASA_L) = ASA_STRANS then
309 
             ExtReg_next(EXTCMD)(EXTCMD_ASA_H downto EXTCMD_ASA_L) <= "000";
310 
        end if;
311 
      end if;
312 
 
313 
 
314 
      -- neue Daten übernehmen
315 
      if ((extsel = '1') and (exti.write_en = '1')) then
316 
        case exti.addr(4 downto 2) is
317 
          when "000" =>
318 
            if ((exti.byte_en(0) = '1')) then
319 
              ExtReg_next(2) <= exti.data(7 downto 0);
320 
            end if;
321 
            if ((exti.byte_en(1) = '1')) then
322 
              ExtReg_next(3) <= exti.data(15 downto 8);
323 
            end if;
324 
            if ((exti.byte_en(2) = '1')) then
325 
              ExtReg_next(2) <= exti.data(23 downto 16);
326 
            end if;
327 
            if ((exti.byte_en(3) = '1')) then
328 
              ExtReg_next(3) <= exti.data(31 downto 24);
329 
            end if;
330 
          when "001" =>
331 
            if ((exti.byte_en(0) = '1')) then
332 
              ExtReg_next(4) <= exti.data(7 downto 0);
333 
            end if;
334 
            if ((exti.byte_en(1) = '1')) then
335 
              ExtReg_next(5) <= exti.data(15 downto 8);
336 
            end if;
337 
            if ((exti.byte_en(2) = '1')) then
338 
              ExtReg_next(6) <= exti.data(23 downto 16);
339 
              newmessage <= '1';
340 
            end if;
341 
            if ((exti.byte_en(3) = '1')) then
342 
              ExtReg_next(7) <= exti.data(31 downto 24);
343 
            end if;
344 
          when "010" =>
345 
            if ((exti.byte_en(0) = '1')) then
346 
              ExtReg_next(8) <= exti.data(7 downto 0);
347 
            end if;
348 
            if ((exti.byte_en(1) = '1')) then
349 
              ExtReg_next(9) <= exti.data(15 downto 8);
350 
            end if;
351 
          when others =>
352 
            null;
353 
        end case;
354 
      end if;
355 
    end process WRITE_REG;
356 
 
357 
-------------------------------------------------------------------------------
358 
-- Lesezugriff auf das Extension Module
359 
-- Wenn das ID-Bit im Config Register gesetzt ist, so wird auf Data 0/1 der
360 
-- Module Type und die Versionsnummer ausgegeben
361 
-- Bei einem Interrupt wird auf DATA0 der Interruptvector ausgegeben
362 
-------------------------------------------------------------------------------
363 
    READ_REG: process (exti, ExtReg, extsel) --DE AccViol)
364 
    begin
365 
      --Defaultwert (Hochohmig)-> neue Konvention, Default auf 0
366 
--      WrBData <= (others => 'Z');
367 
      exto.data <= (others => '0');
368 
 
369 
      messageread <= '0';
370 
      statusread <= '0';
371 
 
372 
      -- Lesezugriff auf das Module? (ohne Access Violation (AccViol))
373 
      if ((extsel = '1') and (exti.write_en = '0')) then
374 
        case exti.addr(4 downto 2) is
375 
          when "000" =>
376 
              if ((exti.byte_en(0) = '1')) then
377 
                statusread <= '1';
378 
              end if;
379 
            exto.data<= ExtReg(3) & ExtReg(2) & ExtReg(1) & ExtReg(0);
380 
          when "001" =>
381 
            if (ExtReg(CONFIGREG)(CONF_ID) = '1') then
382 
              exto.data<= MODULE_VER & MODULE_ID;
383 
            else
384 
              if ((exti.byte_en(2) = '1')) then
385 
                messageread <= '1';
386 
              end if;
387 
              exto.data<= ExtReg(7) & ExtReg(6) & ExtReg(5) & ExtReg(4);
388 
            end if;
389 
          when "010" =>
390 
            exto.data<= "00000000" & "00000000" & ExtReg(9) & ExtReg(8);
391 
          when others =>
392 
            null;
393 
        end case;
394 
      end if;
395 
    end process READ_REG;
396 
 
397 
 
398 
-------------------------------------------------------------------------------
399 
-- Setzen der Status-Bits
400 
-------------------------------------------------------------------------------
401 
    STATUS_EXT: process(ExtReg, RBR, TBR, ParErr, FrameErr, --Data_r,
402 
                        newmessage, messageread, statusread, event, old_statusread)
403 
    begin
404 
      -- Defaultwerte
405 
     -- MsgNxt(7 downto 0) <= ExtReg(MSGREG_LOW);
406 
        --  MsgNxt(15 downto 8) <= ExtReg(MSGREG_HIGH);
407 
    --  CmdNxt(7 downto 0) <= ExtReg(EXTCMD);
408 
  --    CmdNxt(15 downto 8) <= (others =>'0');
409 
 
410 
      StatusNxt(STA_LOOR) <= ExtReg(CONFIGREG)(CONF_LOOW);
411 
      StatusNxt(STA_FSS)  <= ExtReg(STATUSREG)(STA_FSS);      -- Failsafestate
412 
      StatusNxt(STA_RESH) <= '0';                               --not used
413 
      StatusNxt(STA_RESL) <= '0';                               --not used
414 
      StatusNxt(STA_BUSY) <= '0';      -- miniUART is never too busy!
415 
      StatusNxt(STA_ERR)  <= ExtReg(STATUSREG)(STA_ERR);  -- Error occured
416 
      StatusNxt(STA_RDY)  <= '1';                               --not used
417 
      StatusNxt(STA_INT)  <= ExtReg(STATUSREG)(STA_INT);
418 
      IntAckClrNxt         <= ExtReg(CONFIGREG)(CONF_INTA);
419 
 
420 
      StatusNxt(15)          <= '0';    -- not used
421 
      StatusNxt(STA_TRANSERR +8) <= ExtReg(STATUSREG_CUST)(STA_TRANSERR); -- Transmission Error (Frame Error)
422 
      StatusNxt(STA_PARERR+8)   <= ExtReg(STATUSREG_CUST)(STA_PARERR); -- Parity Error
423 
      StatusNxt(STA_EVF+8)      <= ExtReg(STATUSREG_CUST)(STA_EVF);    -- EventFlag
424 
      StatusNxt(STA_OVF+8)      <= ExtReg(STATUSREG_CUST)(STA_OVF);    -- OverflowFlag
425 
      StatusNxt(STA_RBR+8)      <= ExtReg(STATUSREG_CUST)(STA_RBR);     -- Receive Buffer Ready
426 
      StatusNxt(STA_TBR+8)      <= ExtReg(STATUSREG_CUST)(STA_TBR);    -- Transmit Buffer Ready
427 
      StatusNxt(8)           <= '0';    -- not used
428 
 
429 
      -- Nachricht empfangen
430 
      if RBR = RB_READY then
431 
        StatusNxt(STA_RBR+8) <= RB_READY;
432 
        -- Overflow?
433 
        if ExtReg(STATUSREG_CUST)(STA_RBR) = RB_READY then
434 
          StatusNxt(STA_OVF) <= OVERFLOW;
435 
        end if;
436 
        -- übernehmen
437 
   --     MsgNxt <= Data_r;
438 
        -- Parity bzw. Transmission (Frame) Error (nur wenn TrCtrl oder ERRI)
439 
        if (ExtReg(EXTUARTCONF)(EXTCONF_TRCTRL) = TRCTRL_ENA) or (ExtReg(EXTCMD)(EXTCMD_ERRI) = TRCTRL_ENA) then
440 
          StatusNxt(STA_PARERR+8) <= ParErr;
441 
          StatusNxt(STA_TRANSERR +8) <= FrameErr;
442 
          if (ParErr = PARITY_ERROR) or (FrameErr = FRAME_ERROR) then
443 
            StatusNxt(STA_ERR) <= '1';
444 
          end if;
445 
          -- Interrupt auslösen?
446 
          if (ExtReg(EXTCMD)(EXTCMD_ERRI) = TRCTRL_ENA) and ((ParErr = PARITY_ERROR) or (FrameErr = FRAME_ERROR)) then
447 
            StatusNxt(STA_INT) <= '1';
448 
            IntAckClrNxt <= '0';
449 
          end if;
450 
        end if;
451 
      elsif messageread = '1' then
452 
        -- clear receive flags
453 
        StatusNxt(STA_RBR+8) <= not RB_READY;
454 
        StatusNxt(STA_OVF+8) <= not OVERFLOW;
455 
        StatusNxt(STA_PARERR+8) <= not PARITY_ERROR;
456 
        StatusNxt(STA_TRANSERR+8) <= not FRAME_ERROR;
457 
        StatusNxt(STA_ERR) <= '0';
458 
      end if;
459 
 
460 
      -- Nachricht wird gesendet, TBR für eine Taktperiode auf high => signal
461 
-- ist irreführend, es zeigt legilich an, dass mit dem Senden der Nachricht
462 
-- begonnen wurde, nicht dass sie erfolgreich übertragen wurde.
463 
      if TBR = TB_READY then
464 
        StatusNxt(STA_TBR+8) <= TB_READY;
465 
        -- erneutes Senden verhindern!
466 
       -- if ExtReg(EXTCMD)(EXTCMD_ASA_H downto EXTCMD_ASA_L) = ASA_STRANS then
467 
       --   CmdNxt(EXTCMD_ASA_H downto EXTCMD_ASA_L) <= "000";
468 
       -- end if;
469 
      elsif newmessage = '1' then
470 
        -- clear TBR
471 
        StatusNxt(STA_TBR+8) <= not TB_READY;
472 
      end if;
473 
 
474 
      -- Event
475 
      if event = EV_OCC then
476 
        StatusNxt(STA_EVF+8) <= EV_OCC;
477 
        -- Interrupt auslösen
478 
        if ExtReg(EXTCMD)(EXTCMD_EI) = EV_INT then
479 
          StatusNxt(STA_INT) <= '1';
480 
          IntAckClrNxt <= '0';
481 
        end if;
482 
      elsif (old_statusread = '1') and (statusread = '0') then
483 
        StatusNxt(STA_EVF+8) <= not EV_OCC;
484 
      end if;
485 
 
486 
      -- Failsafestate
487 
      if ExtReg(CONFIGREG)(CONF_EFSS) = FAILSAFE then
488 
        StatusNxt(STA_FSS) <= '1';
489 
        StatusNxt(STA_INT) <= '1';
490 
        IntAckClrNxt <= '0';
491 
      else
492 
        StatusNxt(STA_FSS) <= '0';
493 
      end if;
494 
 
495 
      -- Interruptstatus (bei Acknowledge abdrehen)
496 
      if ExtReg(CONFIGREG)(CONF_INTA) = '1' then
497 
        StatusNxt(STA_INT)  <= '0';
498 
        IntAckClrNxt        <= '0';
499 
      end if;
500 
 
501 
    end process STATUS_EXT;
502 
 
503 
 
504 
-------------------------------------------------------------------------------
505 
-- Ein Reset kann durch ein externes Signal oder durch setzen eines Bits im
506 
-- Config-Register ausgelöst werden.
507 
-------------------------------------------------------------------------------
508 
    RESET_EXT: process (exti, ExtReg)
509 
    begin
510 
      -- Defaultwert
511 
      ExtReset <= not RST_ACT;
512 
      if exti.reset = RST_ACT or ExtReg(CONFIGREG)(CONF_SRES)= '1' then
513 
        ExtReset <= RST_ACT;
514 
      end if;
515 
    end process RESET_EXT;
516 
 
517 
 
518 
 
519 
-------------------------------------------------------------------------------
520 
-------------------------------------------------------------------------------
521 
-------------------------------------------------------------------------------
522 
-- Module Specific Part
523 
-------------------------------------------------------------------------------
524 
-------------------------------------------------------------------------------
525 
-------------------------------------------------------------------------------
526 
 
527 
-------------------------------------------------------------------------------
528 
-- Parity berechnen
529 
-------------------------------------------------------------------------------
530 
    PARITY_CALC: process (ExtReg)
531 
--      variable i : integer;
532 
      variable parity : std_logic;
533 
    begin  -- process PARITY_CALC
534 
      parity := '0';
535 
      for i in 15 downto 0 loop
536 
        if to_integer(unsigned(ExtReg(EXTUARTCONF)(EXTCONF_MSGL_H downto EXTCONF_MSGL_L))) < i then
537 
          parity := parity;
538 
        else
539 
                  if i < 8 then
540 
                parity := parity xor ExtReg(MSGREG_LOW)(i);
541 
                  else
542 
                        parity := parity xor ExtReg(MSGREG_HIGH)(i-8);
543 
          end if;
544 
                end if;
545 
      end loop;
546 
 
547 
      -- Odd oder even?
548 
      ParBit <= parity xor ExtReg(EXTUARTCONF)(EXTCONF_PARODD);
549 
    end process PARITY_CALC;
550 
 
551 
-------------------------------------------------------------------------------
552 
-- Output disable (explizit oder im FSS)
553 
-------------------------------------------------------------------------------
554 
    OUTPUT_CONTROL: process (ExtReg)
555 
    begin  -- process FSS_CONTROL
556 
      if (ExtReg(STATUSREG)(STA_FSS) = '1') or (ExtReg(CONFIGREG)(EXTCONF_OUTD) = OUTD_ACT) then
557 
        OutD <= OUTD_ACT;
558 
      else
559 
        OutD <= not OUTD_ACT;
560 
      end if;
561 
    end process OUTPUT_CONTROL;
562 
 
563 
 
564 
-------------------------------------------------------------------------------
565 
-- Interrupt request
566 
-------------------------------------------------------------------------------
567 
 
568 
   INT_CONTROL: process (ExtReg)
569 
   begin  -- process INT_CONTROL
570 
     if ExtReg(STATUSREG)(STA_INT) = '1' then
571 
       exto.intreq <= '1';--EXC_ACT;
572 
     else
573 
       exto.intreq <= '0';--not EXC_ACT;
574 
     end if;
575 
   end process INT_CONTROL;
576 
 
577 
end behaviour;
578 
 
579 
----------------------------------------------------------------------------------
580 
-- END ARCHITECTURE
581 
----------------------------------------------------------------------------------
582 
 
583 
 
584 
 
585 
LIBRARY IEEE;
586 
USE IEEE.std_logic_1164.all;
587 
USE IEEE.std_logic_arith.all;
588 
use IEEE.std_logic_UNSIGNED.all;
589 
 
590 
use work.scarts_core_pkg.all;
591 
use work.scarts_pkg.all;
592 
 
593 
----------------------------------------------------------------------------------
594 
-- ENTITY
595 
----------------------------------------------------------------------------------
596 
entity miniUART_BRG is
597 
 
598 
  port (
599 
    clk : in std_logic;
600 
    reset : in std_logic;
601 
    StartTrans : in std_logic;          -- Transmitterpulse eingeschaltet?
602 
    StartRec : in std_logic;            -- Receiverpulse eingeschaltet?
603 
    UBRS : in std_logic_vector(15 downto 0);  -- Baud Rate Selection Register
604 
                                              -- (12 bit ganzzahlig, 4 bit fraction)
605 
 
606 
    tp : out std_logic;                 -- Transmitterpulse
607 
    rp : out std_logic                  -- Receiverpulse
608 
    );
609 
 
610 
end miniUART_BRG;
611 
 
612 
----------------------------------------------------------------------------------
613 
-- ARCHITECTURE
614 
----------------------------------------------------------------------------------
615 
architecture behaviour of miniUART_BRG is
616 
 
617 
  -- Zählerbreite (11bit aus UBRS + 1bit Überlaufschutz)
618 
  constant COUNTERWIDTH : integer := 12;
619 
  -- Zählerkonstanten
620 
  constant COUNTER_ZERO : std_logic_vector(COUNTERWIDTH-1 downto 0) := (0 => '1', others => '0');
621 
  -- Überlaufregisterbreite (4bit aus UBRS + 1bit Überlauf)
622 
  constant OVERFLOWWIDTH : integer := 6;
623 
 
624 
 
625 
  -- interne Signale zur Zwischenspeicherung der Eingänge
626 
  signal UBRS_i, UBRS_nxt : std_logic_vector(16 downto 0);
627 
 
628 
  -- Zähler
629 
  signal counter : std_logic_vector(COUNTERWIDTH-1 downto 0);
630 
  signal next_counter : std_logic_vector(COUNTERWIDTH-1 downto 0);
631 
 
632 
  -- Überlaufregister
633 
  signal overflow : std_logic_vector(OVERFLOWWIDTH-1 downto 0);
634 
  signal next_overflow : std_logic_vector(OVERFLOWWIDTH-1 downto 0);
635 
 
636 
  -- Transmitpulse oder Receivepulse?
637 
  signal pulse_toggle : std_logic;
638 
  signal next_pulse_toggle : std_logic;
639 
 
640 
begin  -- behaviour
641 
 
642 
  BRG_COUNTER: process (clk, reset)
643 
  begin  -- process BRG_COUNTER
644 
 
645 
    -- ausgeschaltet, entspricht reset
646 
    if reset = RST_ACT then
647 
      counter <= COUNTER_ZERO;
648 
      overflow(4 downto 0) <= (others => '0');-- UBRS(4 downto 0);
649 
      overflow(OVERFLOWWIDTH-1) <= '0';
650 
      UBRS_i(16) <= '0';
651 
      UBRS_i(15 downto 0) <= (others => '1'); --UBRS;          -- UBRS übernehmen
652 
      pulse_toggle <= '0';              -- Transmitter zuerst!
653 
      -- in Betrieb, runterzählen
654 
    elsif (clk'event and clk = '1') then
655 
      counter <= next_counter;
656 
      overflow <= next_overflow;
657 
      UBRS_i <= UBRS_nxt;
658 
      pulse_toggle <= next_pulse_toggle;
659 
    end if;
660 
  end process BRG_COUNTER;
661 
 
662 
 
663 
  BRG_CALC_NEXT: process (counter, overflow, UBRS_i, UBRS, StartTrans,
664 
                          StartRec, pulse_toggle)
665 
  begin  -- process BRG_CALC_NEXT
666 
    -- Defaultwerte
667 
 
668 
    tp <= '0';
669 
    rp <= '0';
670 
    UBRS_nxt <= UBRS_i;
671 
     -- counter weiterzählen
672 
    next_counter <= counter - '1';
673 
    next_overflow <= overflow;
674 
    -- pulse_toggle halten
675 
    next_pulse_toggle <= pulse_toggle;
676 
 
677 
    if (StartTrans /= BRG_ON) and (StartRec /= BRG_ON) then
678 
      next_counter <= COUNTER_ZERO;
679 
      next_overflow(4 downto 0) <= UBRS(4 downto 0);
680 
      next_overflow(OVERFLOWWIDTH-1) <= '0';
681 
      next_pulse_toggle <= '0';
682 
      UBRS_nxt(16) <= '0';
683 
      UBRS_nxt(15 downto 0) <= UBRS;
684 
 -- counter zurücksetzen, neues overflow berechnen
685 
    elsif counter = COUNTER_ZERO then
686 
      next_counter <= UBRS_i(16 downto 5) + overflow(5);
687 
      next_overflow <= (overflow and "011111") + UBRS_i(4 downto 0);
688 
      -- Pulses ausgeben
689 
      tp <= (not pulse_toggle) and StartTrans;
690 
      rp <= pulse_toggle and StartRec;
691 
      next_pulse_toggle <= not pulse_toggle;
692 
    end if;
693 
 
694 
  end process BRG_CALC_NEXT;
695 
 
696 
end behaviour;
697 
 
698 
 
699 
 
700 
 
701 
----------------------------------------------------------------------------------
702 
-- LIBRARY
703 
----------------------------------------------------------------------------------
704 
LIBRARY IEEE;
705 
USE IEEE.std_logic_1164.all;
706 
USE IEEE.std_logic_arith.all;
707 
use work.scarts_core_pkg.all;
708 
use work.scarts_pkg.all;
709 
 
710 
----------------------------------------------------------------------------------
711 
-- ENTITY
712 
----------------------------------------------------------------------------------
713 
entity miniUART_busdriver is
714 
 
715 
  port (
716 
    clk : in std_logic;
717 
    reset : in std_logic;
718 
    OutD : in std_logic;                -- Output disable
719 
    TransEna : in std_logic;            -- Einschalten, von Transmitter
720 
    RecEna : in std_logic;              -- Einschalten, von Receiver
721 
    Data_t : in std_logic;              -- zu sendendes Bit
722 
 
723 
    Data_r : out std_logic;             -- empfangenes Bit
724 
 
725 
    TxD : out std_logic;                -- Sendeleitung
726 
    RxD : in std_logic                  -- Empfangsleitung
727 
    );
728 
 
729 
end miniUART_busdriver;
730 
 
731 
----------------------------------------------------------------------------------
732 
-- ARCHITECTURE
733 
----------------------------------------------------------------------------------
734 
architecture behaviour of miniUART_busdriver is
735 
 
736 
  signal Data_r_nxt : std_logic;
737 
  signal Data_r_int : std_logic;
738 
 
739 
  -- Zwischenpuffer, um Spitzen auszugleichen
740 
  signal buffer1, buffer1_nxt : std_logic;
741 
  signal buffer2, buffer2_nxt : std_logic;
742 
  signal buffer3, buffer3_nxt : std_logic;
743 
 
744 
begin  -- behaviour
745 
 
746 
  BUSDRIVER_BUFFER: process (clk, reset)
747 
  begin  -- process BUSDRIVER_BUFFER
748 
    if reset = RST_ACT then
749 
      buffer1 <= '1';
750 
      buffer2 <= '1';
751 
      buffer3 <= '1';
752 
      Data_r_int <= '1';
753 
    -- Zwischenpuffer der Reihe nach füllen
754 
    elsif (clk'event and clk = '1') then
755 
      buffer1 <= buffer1_nxt;
756 
      buffer2 <= buffer2_nxt;
757 
      buffer3 <= buffer3_nxt;
758 
      Data_r_int <= Data_r_nxt;
759 
    end if;
760 
  end process BUSDRIVER_BUFFER;
761 
 
762 
 
763 
  BUSDRIVER_FILTER: process (RecEna, buffer1, buffer2, buffer3, Data_r_int, RxD)
764 
  begin  -- process BUSDRIVER_FILTER
765 
 
766 
    Data_r_nxt <= Data_r_int;
767 
 
768 
    if RecEna /= BUSDRIVER_ON then
769 
      buffer1_nxt <= '1';
770 
      buffer2_nxt <= '1';
771 
      buffer3_nxt <= '1';
772 
      Data_r_nxt <= '1';
773 
    else
774 
      buffer3_nxt <= buffer2;
775 
      buffer2_nxt <= buffer1;
776 
      buffer1_nxt <= RxD;
777 
     end if;
778 
 
779 
    -- nur bei gleichen Bufferinhalten weitergeben!
780 
    if (buffer3 = '1' and buffer2 = '1' and buffer1 = '1') then
781 
      Data_r_nxt <= '1';
782 
    elsif (buffer3 = '0' and buffer2 = '0' and buffer1 = '0') then
783 
      Data_r_nxt <= '0';
784 
    end if;
785 
  end process BUSDRIVER_FILTER;
786 
 
787 
 
788 
  BUSDRIVER_TRANS: process (TransEna, OutD, Data_t)
789 
  begin  -- process BUSDRIVER_TRANS
790 
    if (TransEna = BUSDRIVER_ON) and (OutD /= OUTD_ACT) then  -- TODO: OutD Konstante!!!
791 
      TxD <= Data_t;
792 
    else  -- interne Signale zur synchronisation der Ausgänge
793 
--       TxD <= 'Z';                      -- Tri-State
794 
       TxD <= '1';                      -- Point2Point
795 
    end if;
796 
  end process BUSDRIVER_TRANS;
797 
 
798 
  Data_r <= Data_r_int;
799 
 
800 
end behaviour;
801 
 
802 
 
803 
 
804 
 
805 
----------------------------------------------------------------------------------
806 
-- LIBRARY
807 
----------------------------------------------------------------------------------
808 
LIBRARY IEEE;
809 
USE IEEE.std_logic_1164.all;
810 
USE IEEE.std_logic_arith.all;
811 
 
812 
use work.scarts_core_pkg.all;
813 
USE work.scarts_pkg.all;
814 
 
815 
----------------------------------------------------------------------------------
816 
-- ENTITY
817 
----------------------------------------------------------------------------------
818 
entity miniUART_control is
819 
 
820 
  port (
821 
    clk : in std_logic;
822 
    reset : in std_logic;
823 
--    MsgLength : in MsgLength_type;
824 
    ParEna : in std_logic;              -- Parity?
825 
    Odd : in std_logic;                 -- Odd or Even Parity?
826 
    AsA : in std_logic_vector(2 downto 0);  -- Assigned Action
827 
    EvS : in std_logic_vector(1 downto 0);  -- Event Selector
828 
 
829 
    Data_r : in Data_type;              -- received Data
830 
    ParBit_r : in std_logic;            -- empfangenes Paritybit
831 
    FrameErr : in std_logic;
832 
    RecComp : in std_logic;             -- Receive Complete
833 
    RecBusy : in std_logic;             -- Reciever Busy (Startbit detected)
834 
 
835 
    TransComp : in std_logic;           -- Transmission complete
836 
 
837 
 
838 
    EnaRec : out std_logic;             -- Enable receiver
839 
    Data_r_out : out Data_type;         -- empfangene Daten
840 
    FrameErr_out : out std_logic;
841 
    ParityErr : out std_logic;
842 
    RBR : out std_logic;                -- Receive Buffer Ready (Rec Complete)
843 
 
844 
    StartTrans : out std_logic;         -- Start Transmitter (halten bis TrComp!)
845 
    TBR : out std_logic;                -- Transmit Buffer Ready (MSGREG read,
846 
                                        -- transmitter started)
847 
    event : out std_logic               -- Selected Event occured!
848 
    );
849 
 
850 
end miniUART_control;
851 
 
852 
----------------------------------------------------------------------------------
853 
-- ARCHITECTURE
854 
----------------------------------------------------------------------------------
855 
architecture behaviour of miniUART_control is
856 
 
857 
  -- interne Signale zur synchronisation der Ausgänge
858 
  signal EnaRec_i : std_logic;
859 
  signal StartTrans_i : std_logic;
860 
  signal EnaRec_old : std_logic;
861 
  signal StartTrans_old : std_logic;
862 
  signal ParityErr_i : std_logic;
863 
 
864 
  signal TBR_i : std_logic;
865 
  signal RBR_i : std_logic;
866 
 
867 
  -- in/out
868 
  signal Data_r_i : Data_type;
869 
  signal FrameErr_i : std_logic;
870 
 
871 
  -- interne Signale zur Zwischenspeicherung der Eingänge
872 
--  signal MsgLength_i : MsgLength_type;
873 
  signal ParEna_i : std_logic;
874 
  signal Odd_i : std_logic;
875 
  signal ParBit_r_i : std_logic;
876 
 
877 
  signal old_TransComp : std_logic;
878 
  signal old_RecBusy : std_logic;
879 
  signal old_RecComp : std_logic;
880 
 
881 
 
882 
  -- Events
883 
  signal event_i : std_logic;
884 
 
885 
begin  -- behaviour
886 
 
887 
  -- empfangene Daten direkt übernehmen
888 
  Data_r_i <= Data_r;
889 
  ParBit_r_i <= ParBit_r;
890 
  FrameErr_i <= FrameErr;
891 
 
892 
-------------------------------------------------------------------------------
893 
-- Control Synchronisierung
894 
-------------------------------------------------------------------------------
895 
  CTRL_SYNC: process (clk, reset)
896 
  begin  -- process CTRL_SYNC
897 
    --reset, alles zurücksetzen
898 
    if reset = RST_ACT then
899 
      Data_r_out <= (others => '0');
900 
      FrameErr_out <= not FRAME_ERROR;
901 
      ParityErr <= not PARITY_ERROR;
902 
      EnaRec <= not RECEIVER_ENABLED;
903 
      EnaRec_old <= not RECEIVER_ENABLED;
904 
      StartTrans <= not BRG_ON;
905 
      StartTrans_old <= not BRG_ON;
906 
      event <= not EV_OCC;
907 
 
908 
      TBR <= TB_READY; -- neue Nachricht annehmen
909 
      RBR <= not RB_READY;
910 
 
911 
      old_TransComp <= not TRANS_COMP;
912 
      old_RecBusy <= not REC_BUSY;
913 
      old_RecComp <= not REC_COMPLETE;
914 
 
915 
--      MsgLength_i <= (others => '0');
916 
      ParEna_i <= not PARITY_ENABLE;
917 
      Odd_i <= '0';
918 
 
919 
    elsif clk'event and clk = '1' then
920 
      -- Daten ausgeben
921 
      Data_r_out <= Data_r_i;
922 
      FrameErr_out <= FrameErr_i;
923 
      ParityErr <= ParityErr_i;
924 
      EnaRec <= EnaRec_i;
925 
      StartTrans <= StartTrans_i;
926 
      EnaRec_old <= EnaRec_i;
927 
      StartTrans_old <= StartTrans_i;
928 
      event <= event_i;
929 
 
930 
      TBR <= TBR_i;
931 
      RBR <= RBR_i;
932 
 
933 
      -- Zustand merken (um Flanke zu erkennen!)
934 
      old_TransComp <= TransComp;
935 
      old_RecBusy <= RecBusy;
936 
      old_RecComp <= RecComp;
937 
 
938 
      -- Daten merken
939 
  --    MsgLength_i <= MsgLength_i;
940 
      ParEna_i <= ParEna_i;
941 
      Odd_i <= Odd_i;
942 
 
943 
      -- Daten übernehmen (beim Einschalten des Receivers)
944 
      if (EnaRec_old /= RECEIVER_ENABLED) and (EnaRec_i = RECEIVER_ENABLED) then
945 
        -- Aktuelle Daten übernehmen
946 
--        MsgLength_i <= MsgLength;
947 
        ParEna_i <= ParEna;
948 
        Odd_i <= Odd;
949 
      end if;
950 
    end if;
951 
  end process CTRL_SYNC;
952 
 
953 
-------------------------------------------------------------------------------
954 
-- Control Logic
955 
-------------------------------------------------------------------------------
956 
  CTRL_LOGIC: process (EvS, AsA, StartTrans_old, EnaRec_old, TransComp, old_TransComp,
957 
                       RecComp, old_RecComp, RecBusy, old_RecBusy)
958 
                   --    ParEna, Odd, ParEna_i, Odd_i)
959 
 
960 
  begin  -- process CTRL_LOGIC
961 
    StartTrans_i <= StartTrans_old;
962 
    EnaRec_i <= EnaRec_old;
963 
    event_i <= not EV_OCC;
964 
 
965 
    TBR_i <= not TB_READY;
966 
    RBR_i <= not RB_READY;
967 
 
968 
-- TRANSMITTER
969 
    -- Transmitter startet (TBR nur 1 clk halten!)
970 
    if (old_TransComp = TRANS_COMP) and (TransComp /= TRANS_COMP) then
971 
      TBR_i <= TB_READY;
972 
 
973 
    -- Transmission completed
974 
    elsif (old_TransComp /= TRANS_COMP) and (TransComp = TRANS_COMP) then
975 
      -- BRG und damit Transmitter ausschalten
976 
      StartTrans_i <= not BRG_ON;
977 
      -- Event signalisieren
978 
      if EvS = EV_TCOMP then
979 
        event_i <= EV_OCC;
980 
        if AsA = ASA_STRANS then
981 
          -- Transmitter starten
982 
          StartTrans_i <= BRG_ON;
983 
        elsif AsA = ASA_EREC then
984 
          -- Receiver einschalten
985 
          EnaRec_i <= RECEIVER_ENABLED;
986 
        elsif AsA = ASA_DREC then
987 
          -- Receiver ausschalten
988 
          EnaRec_i <= not RECEIVER_ENABLED;
989 
        end if;
990 
      end if;
991 
    end if;
992 
 
993 
-- RECEIVER
994 
    -- Startbit detected
995 
    if (old_RecBusy /= REC_BUSY) and (RecBusy = REC_BUSY) then
996 
 
997 
      if EvS = EV_SBD then
998 
        event_i <= EV_OCC;
999 
        if AsA = ASA_DREC then
1000 
          -- Receiver ausschalten
1001 
          EnaRec_i <= not RECEIVER_ENABLED;
1002 
        elsif AsA = ASA_STRANS then
1003 
          -- Transmitter starten
1004 
          StartTrans_i <= BRG_ON;
1005 
        end if;
1006 
      end if;
1007 
 
1008 
      -- ganze Nachricht empfangen (RBR nur 1 clk halten!)
1009 
    elsif (old_RecComp /= REC_COMPLETE) and (RecComp = REC_COMPLETE) then
1010 
      RBR_i <= RB_READY;
1011 
      if EvS = EV_RCOMP then
1012 
        event_i <= EV_OCC;
1013 
        if AsA = ASA_DREC then
1014 
          -- Receiver ausschalten
1015 
          EnaRec_i <= not RECEIVER_ENABLED;
1016 
        elsif AsA = ASA_STRANS then
1017 
          -- Transmitter starten
1018 
          StartTrans_i <= BRG_ON;
1019 
        end if;
1020 
      end if;
1021 
    end if;
1022 
 
1023 
-- NOEVENT
1024 
    if EvS = EV_NONE then
1025 
      if AsA = ASA_STRANS then
1026 
        -- Transmitter starten
1027 
        StartTrans_i <= BRG_ON;
1028 
      elsif AsA = ASA_EREC then
1029 
        -- Receiver einschalten
1030 
        EnaRec_i <= RECEIVER_ENABLED;
1031 
      elsif AsA = ASA_DREC then
1032 
        -- Receiver ausschalten
1033 
        EnaRec_i <= not RECEIVER_ENABLED;
1034 
      end if;
1035 
    end if;
1036 
 
1037 
  end process CTRL_LOGIC;
1038 
 
1039 
-------------------------------------------------------------------------------
1040 
-- Parity
1041 
-------------------------------------------------------------------------------
1042 
  PARITY_CALC: process (Data_r_i, Odd_i, ParBit_r_i, ParEna_i)
1043 
--    variable i : integer;
1044 
    variable parity : std_logic;
1045 
  begin  -- process PARITY_CALC
1046 
    parity := '0';
1047 
 
1048 
--   for i in conv_Integer(unsigned(MsgLength_i)) downto 0 loop
1049 
     for i in 15 downto 0 loop
1050 
       parity := parity xor Data_r_i(i);
1051 
     end loop;
1052 
 
1053 
    -- Odd oder even?
1054 
    if ((parity xor Odd_i) /= ParBit_r_i) and (ParEna_i = PARITY_ENABLE) then
1055 
      ParityErr_i <= PARITY_ERROR;
1056 
    else
1057 
      ParityErr_i <= not PARITY_ERROR;
1058 
    end if;
1059 
  end process PARITY_CALC;
1060 
 
1061 
end behaviour;
1062 
 
1063 
 
1064 
 
1065 
 
1066 
 
1067 
 
1068 
 
1069 
----------------------------------------------------------------------------------
1070 
-- LIBRARY
1071 
----------------------------------------------------------------------------------
1072 
LIBRARY IEEE;
1073 
USE IEEE.std_logic_1164.all;
1074 
USE IEEE.std_logic_arith.all;
1075 
use IEEE.std_logic_UNSIGNED."+";
1076 
use work.scarts_core_pkg.all;
1077 
use work.scarts_pkg.all;
1078 
 
1079 
----------------------------------------------------------------------------------
1080 
-- ENTITY
1081 
----------------------------------------------------------------------------------
1082 
entity miniUART_receiver is
1083 
 
1084 
  port (
1085 
    clk : in std_logic;
1086 
    reset : in std_logic;
1087 
    enable : in std_logic;              -- Receiver eingeschaltet?
1088 
    MsgLength : in MsgLength_type;
1089 
    Stop2 : in std_logic;               -- Zweites Stopbit?
1090 
    ParEna : in std_logic;              -- Parity?
1091 
    rp : in std_logic;                  -- Receivepulse vom BRG
1092 
    RxD : in std_logic;                 -- Empfangseingang
1093 
 
1094 
    Data : out Data_type;
1095 
    ParBit : out std_logic;             -- Empfangenes Paritybit
1096 
    RecEna : out std_logic;             -- Busdriver einschalten
1097 
    StartRecPulse : out std_logic;      -- Receivepulse generieren
1098 
    busy : out std_logic;               -- Receiving / Startbit detected
1099 
    RecComplete : out std_logic;        -- komplettes Frame empfangen
1100 
    FrameErr : out std_logic
1101 
    );
1102 
 
1103 
end miniUART_receiver;
1104 
 
1105 
----------------------------------------------------------------------------------
1106 
-- ARCHITECTURE
1107 
----------------------------------------------------------------------------------
1108 
architecture behaviour of miniUART_receiver is
1109 
 
1110 
  -- max. 20 empfangene Bits (1+16+1+2); 20d = 10100b
1111 
  constant BITCOUNTERWIDTH : integer := 5;
1112 
 
1113 
  -- Bitnummern der Parity/Stopbits
1114 
  constant PARST1 : std_logic_vector(BITCOUNTERWIDTH-1 downto 0) := "10010";
1115 
  constant ST1ST2 : std_logic_vector(BITCOUNTERWIDTH-1 downto 0) := "10011";
1116 
  constant ST2    : std_logic_vector(BITCOUNTERWIDTH-1 downto 0) := "10100";
1117 
 
1118 
 
1119 
  -- Definition der States
1120 
  type rec_states is (DISABLE_S, STARTBITDETECTION_S, RECEIVE_S);
1121 
 
1122 
  signal Rec_State : rec_states;
1123 
  signal next_Rec_State : rec_states;
1124 
 
1125 
  -- interne Signale zur synchronisation der Ausgänge
1126 
  signal ParBit_i : std_logic;
1127 
  signal ParBit_old : std_logic;
1128 
  signal ParEna_i : std_logic;
1129 
  signal Stop2_i : std_logic;
1130 
  signal RecEna_i : std_logic;
1131 
  signal busy_i : std_logic;
1132 
  signal StartRecPulse_i : std_logic;
1133 
  signal RecComplete_i : std_logic;
1134 
  signal FrameErr1_i : std_logic;
1135 
  signal FrameErr2_i : std_logic;
1136 
  signal FrameErr_int : std_logic;
1137 
  signal Data_i : Data_type;
1138 
--  signal Data : Data_type;
1139 
  signal Data_nxt : Data_type;
1140 
 
1141 
  -- interne Signale zur Zwischenspeicherung der Eingänge
1142 
 -- signal RxD_i, RxD_i_nxt : std_logic;
1143 
 
1144 
  -- Bitzähler
1145 
  signal Bitcounter : std_logic_vector(BITCOUNTERWIDTH-1 downto 0);
1146 
  signal next_Bitcounter : std_logic_vector(BITCOUNTERWIDTH-1 downto 0);
1147 
 
1148 
  -- Nachrichtenlänge
1149 
  signal Length : std_logic_vector(3 downto 0);
1150 
  signal Length_nxt : std_logic_vector(3 downto 0);
1151 
--  signal Length : integer;
1152 
 
1153 
  -- alter Empfangswert
1154 
  signal old_RxD : std_logic;
1155 
 
1156 
  -- alter Pulsewert
1157 
--  signal old_rp : std_logic;
1158 
 
1159 
begin  -- behaviour
1160 
 
1161 
  Data <= Data_i;
1162 
 
1163 
  REC_STATECHANGE: process (clk, reset)
1164 
  begin  -- process REC_STATECHANGE
1165 
    -- Receiver ausgeschalten, kommt einem reset gleich
1166 
    if reset = RST_ACT then
1167 
      RecEna <= not BUSDRIVER_ON;
1168 
      StartRecPulse <= not BRG_ON;
1169 
      busy <= not REC_BUSY;
1170 
      RecComplete <= not REC_COMPLETE;
1171 
      Bitcounter <= (others => '0');
1172 
      Data_i <= (others => '0');
1173 
      ParBit <= '0';
1174 
      FrameErr_int <= not FRAME_ERROR;
1175 
      ParBit_old <= '0';
1176 
      old_RxD <= '1';
1177 
      Rec_State <= DISABLE_S;
1178 
      Length <= (others => '0');
1179 
    -- Signale ausgeben, Statechange
1180 
    elsif (clk'event and clk = '1') then
1181 
      Bitcounter <= next_Bitcounter;
1182 
      RecEna <= RecEna_i;
1183 
      StartRecPulse <= StartRecPulse_i;
1184 
      busy <= busy_i;
1185 
      RecComplete <= RecComplete_i;
1186 
      ParBit <= ParBit_i;
1187 
      ParBit_old <= ParBit_i;
1188 
      FrameErr_int <= FrameErr1_i or FrameErr2_i;
1189 
      Data_i <= Data_nxt;
1190 
      -- Empfangszustand merken (um Flanke zu erkennen!)
1191 
      old_RxD <= RxD;
1192 
      Rec_State <= next_Rec_State;
1193 
      Length <= Length_nxt;
1194 
    end if;
1195 
 
1196 
  end process REC_STATECHANGE;
1197 
 
1198 
 
1199 
 
1200 
  REC_STATEMACHINE: process (enable, MsgLength, ParEna, Stop2, ParEna_i, Stop2_i,
1201 
                              Length, Rec_State, Bitcounter, RxD, Data_i,
1202 
                             ParBit_old, FrameErr_int, old_RxD, rp)
1203 
  begin  -- process REC_STATEMACHINE
1204 
 
1205 
    -- Defaultwerte
1206 
    RecEna_i <= not BUSDRIVER_ON;
1207 
    StartRecPulse_i <= not BRG_ON;
1208 
    busy_i <= not REC_BUSY;
1209 
    RecComplete_i <= not REC_COMPLETE;
1210 
    next_Bitcounter <= Bitcounter;
1211 
    ParEna_i <= ParEna;
1212 
    Stop2_i <= Stop2;
1213 
    Data_nxt <= Data_i;
1214 
    ParBit_i <= ParBit_old;
1215 
    FrameErr1_i <= FrameErr_int;
1216 
    FrameErr2_i <= FrameErr_int;
1217 
    Length_nxt <= Length;
1218 
 
1219 
    case Rec_State is
1220 
      when DISABLE_S =>
1221 
        Data_nxt <= (others => '0');
1222 
        ParBit_i <= '0';
1223 
        FrameErr1_i <= not FRAME_ERROR;
1224 
        FrameErr2_i <= not FRAME_ERROR;
1225 
        next_Rec_State <= DISABLE_S;
1226 
        next_Bitcounter <= (others => '0');
1227 
        -- Receiver eingeschalten
1228 
        if enable = RECEIVER_ENABLED then
1229 
          Length_nxt <= MsgLength; -- Nachrichtenlänge
1230 
          ParEna_i <= ParEna;
1231 
          Stop2_i <= Stop2;
1232 
          RecEna_i <= BUSDRIVER_ON;
1233 
          next_Rec_State <= STARTBITDETECTION_S;
1234 
        end if;
1235 
 
1236 
 
1237 
      when STARTBITDETECTION_S =>
1238 
        Data_nxt <= (others => '0');
1239 
        ParBit_i <= '0';
1240 
        FrameErr1_i <= '0';
1241 
        FrameErr2_i <= '0';
1242 
 
1243 
        RecEna_i <= BUSDRIVER_ON;       -- Bustreiber einschalten
1244 
        next_Rec_State <= STARTBITDETECTION_S;
1245 
        next_Bitcounter <= (others => '0');
1246 
        if (RxD = '0') and (old_RxD = '1') then -- Startbit empfangen!
1247 
          StartRecPulse_i <= BRG_ON;    -- Receivepulse generieren
1248 
          busy_i <= REC_BUSY;           -- working
1249 
          next_Bitcounter <= Bitcounter + '1';
1250 
          next_Rec_State <= RECEIVE_S;
1251 
        end if;
1252 
 
1253 
      when RECEIVE_S =>
1254 
        next_Rec_State <= RECEIVE_S;
1255 
        RecEna_i <= BUSDRIVER_ON;       -- Bustreiber einschalten
1256 
        StartRecPulse_i <= BRG_ON;      -- Receivepulse generieren
1257 
        busy_i <= REC_BUSY;             -- Beschäftigt
1258 
        next_Bitcounter <= Bitcounter;
1259 
        if rp = '1' then
1260 
--          RxD_i_nxt <= RxD;
1261 
          next_Bitcounter <= Bitcounter +1 ;
1262 
--        end if;    -
1263 
--        next_Bitcounter <= Bitcounter + '1';
1264 
        case Bitcounter is
1265 
          when "00000" =>               -- sollte nicht auftreten!!!
1266 
            assert false
1267 
              report "Wait on first Receceive Impuls -> Recieve Startbit"
1268 
              severity NOTE;
1269 
 
1270 
          when "00001" =>               -- Startbit
1271 
            null;
1272 
 
1273 
          -- Daten
1274 
          when "00010" =>               -- Bit 0
1275 
            Data_nxt(0) <= RxD;
1276 
            if Length = "0000" then
1277 
              next_Bitcounter <= PARST1;
1278 
            end if;
1279 
          when "00011" =>               -- Bit 1
1280 
            Data_nxt(1) <= RxD;
1281 
            if Length = "0001" then
1282 
              next_Bitcounter <= PARST1;
1283 
            end if;
1284 
          when "00100" =>               -- Bit 2
1285 
            Data_nxt(2) <= RxD;
1286 
            if Length = "0010" then
1287 
              next_Bitcounter <= PARST1;
1288 
            end if;
1289 
          when "00101" =>               -- Bit 3
1290 
            Data_nxt(3) <= RxD;
1291 
            if Length = "0011" then
1292 
              next_Bitcounter <= PARST1;
1293 
            end if;
1294 
          when "00110" =>               -- Bit 4
1295 
            Data_nxt(4) <= RxD;
1296 
            if Length = "0100" then
1297 
              next_Bitcounter <= PARST1;
1298 
            end if;
1299 
          when "00111" =>               -- Bit 5
1300 
            Data_nxt(5) <= RxD;
1301 
            if Length = "0101" then
1302 
              next_Bitcounter <= PARST1;
1303 
            end if;
1304 
          when "01000" =>               -- Bit 6
1305 
            Data_nxt(6) <= RxD;
1306 
            if Length = "0110" then
1307 
              next_Bitcounter <= PARST1;
1308 
            end if;
1309 
          when "01001" =>               -- Bit 7
1310 
            Data_nxt(7) <= RxD;
1311 
            if Length = "0111" then
1312 
              next_Bitcounter <= PARST1;
1313 
            end if;
1314 
          when "01010" =>               -- Bit 8
1315 
            Data_nxt(8) <= RxD;
1316 
            if Length = "1000" then
1317 
              next_Bitcounter <= PARST1;
1318 
            end if;
1319 
          when "01011" =>               -- Bit 9
1320 
            Data_nxt(9) <= RxD;
1321 
            if Length = "1001" then
1322 
              next_Bitcounter <= PARST1;
1323 
            end if;
1324 
          when "01100" =>               -- Bit 10
1325 
            Data_nxt(10) <= RxD;
1326 
            if Length = "1010" then
1327 
              next_Bitcounter <= PARST1;
1328 
            end if;
1329 
          when "01101" =>               -- Bit 11
1330 
            Data_nxt(11) <= RxD;
1331 
            if Length = "1011" then
1332 
              next_Bitcounter <= PARST1;
1333 
            end if;
1334 
          when "01110" =>               -- Bit 12
1335 
            Data_nxt(12) <= RxD;
1336 
            if Length = "1100" then
1337 
              next_Bitcounter <= PARST1;
1338 
            end if;
1339 
          when "01111" =>               -- Bit 13
1340 
            Data_nxt(13) <= RxD;
1341 
            if Length = "1101" then
1342 
              next_Bitcounter <= PARST1;
1343 
            end if;
1344 
          when "10000" =>               -- Bit 14
1345 
            Data_nxt(14) <= RxD;
1346 
            if Length = "1110" then
1347 
              next_Bitcounter <= PARST1;
1348 
            end if;
1349 
          when "10001" =>               -- Bit 15
1350 
            Data_nxt(15) <= RxD;
1351 
            if Length = "1111" then
1352 
              next_Bitcounter <= PARST1;
1353 
            end if;
1354 
 
1355 
          -- Paritybit
1356 
          when PARST1 =>               -- Parity oder 1. Stopbit
1357 
            if ParEna_i = PARITY_ENABLE then
1358 
              ParBit_i <= RxD;
1359 
            else
1360 
              FrameErr1_i <= not RxD;
1361 
              if Stop2_i /= SECOND_STOPBIT then
1362 
                next_Rec_State <= DISABLE_S; -- fertig
1363 
                RecComplete_i <= REC_COMPLETE;
1364 
                StartRecPulse_i <= not BRG_ON;
1365 
                next_Bitcounter <= (others => '0');
1366 
              end if;
1367 
            end if;
1368 
 
1369 
          -- Stopbits
1370 
          when ST1ST2 =>                -- 1. oder 2. Stopbit
1371 
            FrameErr2_i <= not RxD;
1372 
            if (ParEna_i /= PARITY_ENABLE) or (Stop2_i /= SECOND_STOPBIT) then
1373 
              next_Rec_State <= DISABLE_S; -- fertig
1374 
              RecComplete_i <= REC_COMPLETE;
1375 
              StartRecPulse_i <= not BRG_ON;
1376 
              next_Bitcounter <= (others => '0');
1377 
            end if;
1378 
 
1379 
          when ST2 =>                   -- 2. Stopbit
1380 
            FrameErr1_i <= not RxD; -- fertig
1381 
            next_Rec_State <= DISABLE_S; -- fertig
1382 
            RecComplete_i <= REC_COMPLETE;
1383 
            StartRecPulse_i <= not BRG_ON;
1384 
            next_Bitcounter <= (others => '0');
1385 
 
1386 
          when others =>                -- nicht erreicht!
1387 
            next_Rec_State <= DISABLE_S;
1388 
            RecComplete_i <= REC_COMPLETE;
1389 
            StartRecPulse_i <= not BRG_ON;
1390 
            next_Bitcounter <= (others => '0');
1391 
 
1392 
            assert false
1393 
              report "Bitcounter overrun (miniUART_receiver.vhd)!!!"
1394 
              severity ERROR;
1395 
 
1396 
        end case;
1397 
        end if;
1398 
      when others =>                    --DISABLE_S
1399 
        next_Rec_State <= DISABLE_S;
1400 
    end case;
1401 
  end process REC_STATEMACHINE;
1402 
 
1403 
  FrameErr <=        FrameErr_int;
1404 
end behaviour;
1405 
 
1406 
 
1407 
 
1408 
----------------------------------------------------------------------------------
1409 
-- LIBRARY
1410 
----------------------------------------------------------------------------------
1411 
LIBRARY IEEE;
1412 
USE IEEE.std_logic_1164.all;
1413 
USE IEEE.std_logic_arith.all;
1414 
use IEEE.std_logic_UNSIGNED.all;
1415 
--use IEEE.std_logic_UNSIGNED."-";
1416 
 
1417 
use work.scarts_core_pkg.all;
1418 
use work.scarts_pkg.all;
1419 
 
1420 
----------------------------------------------------------------------------------
1421 
-- ENTITY
1422 
----------------------------------------------------------------------------------
1423 
entity miniUART_transmitter is
1424 
 
1425 
  port (
1426 
    clk : in std_logic;
1427 
    reset : in std_logic;
1428 
    MsgLength : in MsgLength_type;
1429 
    Stop2 : in std_logic;               -- Zweites Stopbit?
1430 
    ParEna : in std_logic;              -- Parity?
1431 
    ParBit : in std_logic;              -- Vorberechnetes Paritybit
1432 
    Data : in Data_type;
1433 
    tp : in std_logic;                  -- Transmitpulse vom BRG
1434 
 
1435 
    TransEna : out std_logic;           -- Busdriver einschalten
1436 
    TrComp : out std_logic;              -- Transmission complete
1437 
    TxD : out std_logic                 -- Sendeausgang
1438 
    );
1439 
 
1440 
end miniUART_transmitter;
1441 
 
1442 
----------------------------------------------------------------------------------
1443 
-- ARCHITECTURE
1444 
----------------------------------------------------------------------------------
1445 
architecture behaviour of miniUART_transmitter is
1446 
 
1447 
  -- Definition der States
1448 
  type trans_states is (START_S, DATA_S, PARITY_S, STOP_S);
1449 
 
1450 
  signal Trans_State : trans_states;
1451 
  signal next_Trans_State : trans_states;
1452 
 
1453 
  -- interne Signale zur synchronisation der Ausgänge
1454 
  signal TxD_i : std_logic;
1455 
  signal TransEna_i : std_logic;
1456 
  signal TrComp_i : std_logic;
1457 
  signal TxD_old : std_logic;
1458 
  signal TransEna_old : std_logic;
1459 
  signal TrComp_old : std_logic;
1460 
 
1461 
  -- interne Signale zur Zwischenspeicherung der Eingänge
1462 
  signal MsgLength_i : MsgLength_type;
1463 
  signal MsgLength_i_nxt : MsgLength_type;
1464 
  signal Stop2_i : std_logic;
1465 
  signal Stop2_i_nxt : std_logic;
1466 
  signal ParEna_i : std_logic;
1467 
  signal ParEna_i_nxt : std_logic;
1468 
  signal ParBit_i : std_logic;
1469 
  signal ParBit_i_nxt : std_logic;
1470 
  signal Data_i : Data_type;
1471 
  signal Data_nxt : Data_type;
1472 
 
1473 
  -- Bitzähler
1474 
  signal Bitcounter : MsgLength_type;
1475 
  signal next_Bitcounter : MsgLength_type;
1476 
 
1477 
  -- Stopzähler (00: 1. Stopbit; 01: 2. Stopbit oder Ende; 10: Ende)
1478 
  signal Stopcounter : std_logic_vector(1 downto 0);
1479 
  signal next_Stopcounter : std_logic_vector(1 downto 0);
1480 
 
1481 
begin  -- behaviour
1482 
 
1483 
  TRANS_OUTPUT : process (clk, reset)
1484 
  begin  -- process TRANS_OUTPUT
1485 
    -- Reset, setzt alles auf Standardwerte
1486 
    if reset = RST_ACT then
1487 
      TxD <= '1';
1488 
      TransEna <= not BUSDRIVER_ON;
1489 
      TrComp <= TRANS_COMP;
1490 
      TxD_old <= '1';
1491 
      TransEna_old <= not BUSDRIVER_ON;
1492 
      TrComp_old <= TRANS_COMP;
1493 
 
1494 
      Data_i <= (others => '1');
1495 
      MsgLength_i <= (others => '0');
1496 
 
1497 
      Bitcounter <= (others => '0');
1498 
      Stopcounter <= (others => '0');
1499 
      Trans_State <= START_S;
1500 
 
1501 
      Stop2_i <= '0';
1502 
      ParBit_i <= '0';
1503 
      ParEna_i <= '0';
1504 
 
1505 
    elsif (clk'event and clk = '1') then
1506 
      TxD <= TxD_old;
1507 
      TransEna <= TransEna_old;
1508 
      TrComp <= TrComp_old;
1509 
 
1510 
      Data_i <= Data_nxt;
1511 
      MsgLength_i <= MsgLength_i_nxt;
1512 
 
1513 
      Bitcounter <= Bitcounter;
1514 
      Stopcounter <= Stopcounter;
1515 
      Trans_State <= Trans_State;
1516 
 
1517 
      Stop2_i <= Stop2_i_nxt;
1518 
      ParBit_i <= ParBit_i_nxt;
1519 
      ParEna_i <= ParEna_i_nxt;
1520 
 
1521 
      -- Bei Transmitpulse: ausgeben, Zustandswechsel
1522 
      if tp = '1' then
1523 
        TxD <= TxD_i;
1524 
        TransEna <= TransEna_i;
1525 
        TrComp <= TrComp_i;
1526 
        TxD_old <= TxD_i;
1527 
        TransEna_old <= TransEna_i;
1528 
        TrComp_old <= TrComp_i;
1529 
 
1530 
        Bitcounter <= next_Bitcounter;   -- Datenbits mitzählen
1531 
        Stopcounter <= next_Stopcounter;  -- Stopbits mitzählen
1532 
 
1533 
        Trans_State <= next_Trans_State;  -- Zustandswechsel
1534 
 
1535 
      end if;
1536 
    end if;
1537 
  end process TRANS_OUTPUT;
1538 
 
1539 
 
1540 
 
1541 
  TRANS_STATEMACHINE: process (Trans_State, Bitcounter, Stopcounter,
1542 
                               MsgLength, MsgLength_i, Data, Data_i,
1543 
                               ParEna, ParEna_i, ParBit, ParBit_i,
1544 
                               Stop2, Stop2_i)
1545 
  begin  -- process TRANS_STATEMACHINE
1546 
    -- Defaultwerte (halten)
1547 
    Data_nxt <= Data_i;
1548 
    MsgLength_i_nxt <= MsgLength_i;
1549 
    ParEna_i_nxt <= ParEna_i;
1550 
    ParBit_i_nxt <= ParBit_i;
1551 
    Stop2_i_nxt <= Stop2_i;
1552 
 
1553 
 
1554 
    case Trans_State is
1555 
      when DATA_S =>
1556 
        TrComp_i <= not TRANS_COMP;
1557 
        TransEna_i <= BUSDRIVER_ON;
1558 
        next_Bitcounter <= Bitcounter + '1';
1559 
        next_Stopcounter <= (others => '0');
1560 
 
1561 
        -- letztes Bit des Datenwortes
1562 
        if Bitcounter = MsgLength_i then
1563 
          TxD_i <= Data_i(conv_Integer(unsigned(Bitcounter)));
1564 
 
1565 
          if ParEna_i = PARITY_ENABLE then
1566 
            next_Trans_State <= PARITY_S;
1567 
          else
1568 
            next_Trans_State <= STOP_S;
1569 
          end if;
1570 
 
1571 
        -- irgendeine Position im Datenwort
1572 
        else
1573 
          TxD_i <= Data_i(conv_Integer(unsigned(Bitcounter)));
1574 
          next_Trans_State <= DATA_S;
1575 
        end if;
1576 
 
1577 
      when PARITY_S =>
1578 
        TxD_i <= ParBit_i;
1579 
        TrComp_i <= not TRANS_COMP;
1580 
        TransEna_i <= BUSDRIVER_ON;
1581 
        next_Bitcounter <= (others => '0');
1582 
        next_Stopcounter <= (others => '0');
1583 
 
1584 
        next_Trans_State <= STOP_S;
1585 
 
1586 
      when STOP_S =>
1587 
        TxD_i <= '1';
1588 
 
1589 
        next_Bitcounter <= (others => '0');
1590 
        next_Stopcounter <= Stopcounter + '1';
1591 
 
1592 
        case Stopcounter is
1593 
          -- erstes Stopbit
1594 
          when "00" =>
1595 
            TrComp_i <= not TRANS_COMP;
1596 
            TransEna_i <= BUSDRIVER_ON;
1597 
            next_Trans_State <= STOP_S;
1598 
 
1599 
          -- zweites Stopbit oder Ende
1600 
          when "01" =>
1601 
            if Stop2_i = SECOND_STOPBIT then
1602 
              TrComp_i <= not TRANS_COMP;
1603 
              TransEna_i <= BUSDRIVER_ON;
1604 
              next_Trans_State <= STOP_S;
1605 
            else
1606 
              TrComp_i <= TRANS_COMP;
1607 
              TransEna_i <= not BUSDRIVER_ON;
1608 
              next_Trans_State <= START_S;
1609 
            end if;
1610 
 
1611 
          -- Ende
1612 
          when others =>
1613 
            TrComp_i <= TRANS_COMP;
1614 
            TransEna_i <= not BUSDRIVER_ON;
1615 
            next_Trans_State <= START_S;
1616 
        end case;
1617 
 
1618 
      when others =>                    -- START_S
1619 
        TxD_i <= '0';
1620 
 
1621 
        -- halten, erst nach Datenübernahme freigeben (DATA_S)
1622 
        TrComp_i <= TRANS_COMP;
1623 
 
1624 
        TransEna_i <= BUSDRIVER_ON;
1625 
 
1626 
        -- neue Daten holen
1627 
        Data_nxt <= Data;
1628 
        MsgLength_i_nxt <= MsgLength;
1629 
        ParEna_i_nxt <= ParEna;
1630 
        ParBit_i_nxt <= ParBit;
1631 
        Stop2_i_nxt <= Stop2;
1632 
 
1633 
        next_Bitcounter <= (others => '0');
1634 
        next_Stopcounter <= (others => '0');
1635 
        next_Trans_State <= DATA_S;
1636 
 
1637 
    end case;
1638 
  end process TRANS_STATEMACHINE;
1639 
 
1640 
end behaviour;

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